diff options
author | Divya Singhatwaria <dsinghatwari@nvidia.com> | 2021-01-27 11:05:32 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2021-03-17 12:54:54 -0400 |
commit | 9170f2b77cba9aedd957acdde7c758e81e073cc0 (patch) | |
tree | 661d7acd1c425b7e5601e5b18d394fa9bd10a016 /drivers/gpu/nvgpu | |
parent | 7882f15ff63199a517852760f5686ecd0b886123 (diff) |
gpu: nvgpu: remove ZBC save/restore by PMU
- ZBC save/restore registers are removed in GP10B PMU ucode.
- These registers are saved/restored from CTXSW ucode during
ELPG entry/exit.
- Accessing the ZBC registers will cause PMU EXTERR error.
- To resolve this, ZBC functionality is removed from GP10B
feature list in PMU ucode.
- From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false
for GP10B
- Updated the GP10B PMU app version for the ucode:
https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260
P4 CL link related to this PMU ucode change:
https://p4sw-swarm.nvidia.com/changes/29594520
Bug 3233071
Bug 200696431
Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2476259
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index 56e79f5a..da77f984 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -40,7 +40,7 @@ | |||
40 | #define APP_VERSION_GV11B 25005711U | 40 | #define APP_VERSION_GV11B 25005711U |
41 | #define APP_VERSION_GV10X 23647491U | 41 | #define APP_VERSION_GV10X 23647491U |
42 | #define APP_VERSION_GP10X 24076634U | 42 | #define APP_VERSION_GP10X 24076634U |
43 | #define APP_VERSION_GP10B 23782727U | 43 | #define APP_VERSION_GP10B 29594520U |
44 | #define APP_VERSION_GM20B 20490253U | 44 | #define APP_VERSION_GM20B 20490253U |
45 | 45 | ||
46 | /* PMU version specific functions */ | 46 | /* PMU version specific functions */ |
@@ -1155,7 +1155,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1155 | set_perfmon_cntr_group_id_v2; | 1155 | set_perfmon_cntr_group_id_v2; |
1156 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1156 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1157 | g->pmu_ver_cmd_id_zbc_table_update = 16; | 1157 | g->pmu_ver_cmd_id_zbc_table_update = 16; |
1158 | __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true); | 1158 | __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, false); |
1159 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1159 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1160 | pmu_cmdline_size_v4; | 1160 | pmu_cmdline_size_v4; |
1161 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1161 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |