diff options
author | Seema Khowala <seemaj@nvidia.com> | 2016-10-12 18:16:47 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-18 19:46:15 -0500 |
commit | 911dcedb489ebef5758e5533f73e8653cc7770b7 (patch) | |
tree | 15a95a842f5a24af0a8d88c605c02b86d3ab4101 /drivers/gpu/nvgpu | |
parent | 28fb1de00a907719a02cee62c7e7f3a0aee7075f (diff) |
gpu: nvgpu: support t19x zbc
Added infrastructure for supporting
new zbc features
JIRA GV11B-9
Change-Id: Id8408348759488e8b0393dd89dd0faacfb111f01
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1235525
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 42 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 17 |
4 files changed, 69 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index 26eea610..aa2c4959 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2016, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2011-2017, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -1413,6 +1413,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
1413 | } | 1413 | } |
1414 | break; | 1414 | break; |
1415 | case GK20A_ZBC_TYPE_DEPTH: | 1415 | case GK20A_ZBC_TYPE_DEPTH: |
1416 | case T19X_ZBC: | ||
1416 | zbc_val->depth = set_table_args->depth; | 1417 | zbc_val->depth = set_table_args->depth; |
1417 | break; | 1418 | break; |
1418 | default: | 1419 | default: |
@@ -1452,6 +1453,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
1452 | } | 1453 | } |
1453 | break; | 1454 | break; |
1454 | case GK20A_ZBC_TYPE_DEPTH: | 1455 | case GK20A_ZBC_TYPE_DEPTH: |
1456 | case T19X_ZBC: | ||
1455 | query_table_args->depth = zbc_tbl->depth; | 1457 | query_table_args->depth = zbc_tbl->depth; |
1456 | break; | 1458 | break; |
1457 | case GK20A_ZBC_TYPE_INVALID: | 1459 | case GK20A_ZBC_TYPE_INVALID: |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a78ff506..00a580dd 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -142,6 +142,9 @@ struct gpu_ops { | |||
142 | void (*set_zbc_depth_entry)(struct gk20a *g, | 142 | void (*set_zbc_depth_entry)(struct gk20a *g, |
143 | struct zbc_entry *depth_val, | 143 | struct zbc_entry *depth_val, |
144 | u32 index); | 144 | u32 index); |
145 | void (*set_zbc_s_entry)(struct gk20a *g, | ||
146 | struct zbc_entry *s_val, | ||
147 | u32 index); | ||
145 | void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr); | 148 | void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr); |
146 | void (*sync_debugfs)(struct gk20a *g); | 149 | void (*sync_debugfs)(struct gk20a *g); |
147 | void (*init_fs_state)(struct gk20a *g); | 150 | void (*init_fs_state)(struct gk20a *g); |
@@ -223,13 +226,23 @@ struct gpu_ops { | |||
223 | struct zbc_entry *color_val, u32 index); | 226 | struct zbc_entry *color_val, u32 index); |
224 | int (*add_zbc_depth)(struct gk20a *g, struct gr_gk20a *gr, | 227 | int (*add_zbc_depth)(struct gk20a *g, struct gr_gk20a *gr, |
225 | struct zbc_entry *depth_val, u32 index); | 228 | struct zbc_entry *depth_val, u32 index); |
229 | int (*add_zbc_s)(struct gk20a *g, struct gr_gk20a *gr, | ||
230 | struct zbc_entry *s_val, u32 index); | ||
226 | int (*zbc_set_table)(struct gk20a *g, struct gr_gk20a *gr, | 231 | int (*zbc_set_table)(struct gk20a *g, struct gr_gk20a *gr, |
227 | struct zbc_entry *zbc_val); | 232 | struct zbc_entry *zbc_val); |
228 | int (*zbc_query_table)(struct gk20a *g, struct gr_gk20a *gr, | 233 | int (*zbc_query_table)(struct gk20a *g, struct gr_gk20a *gr, |
229 | struct zbc_query_params *query_params); | 234 | struct zbc_query_params *query_params); |
235 | int (*zbc_s_query_table)(struct gk20a *g, struct gr_gk20a *gr, | ||
236 | struct zbc_query_params *query_params); | ||
237 | int (*load_zbc_s_default_tbl)(struct gk20a *g, | ||
238 | struct gr_gk20a *gr); | ||
239 | int (*load_zbc_s_tbl)(struct gk20a *g, | ||
240 | struct gr_gk20a *gr); | ||
230 | void (*pmu_save_zbc)(struct gk20a *g, u32 entries); | 241 | void (*pmu_save_zbc)(struct gk20a *g, u32 entries); |
231 | int (*add_zbc)(struct gk20a *g, struct gr_gk20a *gr, | 242 | int (*add_zbc)(struct gk20a *g, struct gr_gk20a *gr, |
232 | struct zbc_entry *zbc_val); | 243 | struct zbc_entry *zbc_val); |
244 | bool (*add_zbc_type_s)(struct gk20a *g, struct gr_gk20a *gr, | ||
245 | struct zbc_entry *zbc_val, int *ret_val); | ||
233 | u32 (*pagepool_default_size)(struct gk20a *g); | 246 | u32 (*pagepool_default_size)(struct gk20a *g); |
234 | int (*init_ctx_state)(struct gk20a *g); | 247 | int (*init_ctx_state)(struct gk20a *g); |
235 | int (*alloc_gr_ctx)(struct gk20a *g, | 248 | int (*alloc_gr_ctx)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f1ef8be2..c5e927c1 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4018,7 +4018,8 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | |||
4018 | { | 4018 | { |
4019 | struct zbc_color_table *c_tbl; | 4019 | struct zbc_color_table *c_tbl; |
4020 | struct zbc_depth_table *d_tbl; | 4020 | struct zbc_depth_table *d_tbl; |
4021 | u32 i, ret = -ENOMEM; | 4021 | u32 i; |
4022 | int ret = -ENOMEM; | ||
4022 | bool added = false; | 4023 | bool added = false; |
4023 | u32 entries; | 4024 | u32 entries; |
4024 | 4025 | ||
@@ -4094,6 +4095,16 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | |||
4094 | gr->max_used_depth_index++; | 4095 | gr->max_used_depth_index++; |
4095 | } | 4096 | } |
4096 | break; | 4097 | break; |
4098 | case T19X_ZBC: | ||
4099 | if (g->ops.gr.add_zbc_type_s) { | ||
4100 | added = g->ops.gr.add_zbc_type_s(g, gr, zbc_val, &ret); | ||
4101 | } else { | ||
4102 | gk20a_err(dev_from_gk20a(g), | ||
4103 | "invalid zbc table type %d", zbc_val->type); | ||
4104 | ret = -EINVAL; | ||
4105 | goto err_mutex; | ||
4106 | } | ||
4107 | break; | ||
4097 | default: | 4108 | default: |
4098 | gk20a_err(dev_from_gk20a(g), | 4109 | gk20a_err(dev_from_gk20a(g), |
4099 | "invalid zbc table type %d", zbc_val->type); | 4110 | "invalid zbc table type %d", zbc_val->type); |
@@ -4150,6 +4161,16 @@ int gr_gk20a_query_zbc(struct gk20a *g, struct gr_gk20a *gr, | |||
4150 | query_params->format = gr->zbc_dep_tbl[index].format; | 4161 | query_params->format = gr->zbc_dep_tbl[index].format; |
4151 | query_params->ref_cnt = gr->zbc_dep_tbl[index].ref_cnt; | 4162 | query_params->ref_cnt = gr->zbc_dep_tbl[index].ref_cnt; |
4152 | break; | 4163 | break; |
4164 | case T19X_ZBC: | ||
4165 | if (g->ops.gr.zbc_s_query_table) { | ||
4166 | return g->ops.gr.zbc_s_query_table(g, gr, | ||
4167 | query_params); | ||
4168 | } else { | ||
4169 | gk20a_err(dev_from_gk20a(g), | ||
4170 | "invalid zbc table type\n"); | ||
4171 | return -EINVAL; | ||
4172 | } | ||
4173 | break; | ||
4153 | default: | 4174 | default: |
4154 | gk20a_err(dev_from_gk20a(g), | 4175 | gk20a_err(dev_from_gk20a(g), |
4155 | "invalid zbc table type\n"); | 4176 | "invalid zbc table type\n"); |
@@ -4192,6 +4213,13 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr) | |||
4192 | if (ret) | 4213 | if (ret) |
4193 | return ret; | 4214 | return ret; |
4194 | } | 4215 | } |
4216 | |||
4217 | if (g->ops.gr.load_zbc_s_tbl) { | ||
4218 | ret = g->ops.gr.load_zbc_s_tbl(g, gr); | ||
4219 | if (ret) | ||
4220 | return ret; | ||
4221 | } | ||
4222 | |||
4195 | return 0; | 4223 | return 0; |
4196 | } | 4224 | } |
4197 | 4225 | ||
@@ -4221,7 +4249,7 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
4221 | zbc_val.color_ds[i] = 0; | 4249 | zbc_val.color_ds[i] = 0; |
4222 | zbc_val.color_l2[i] = 0; | 4250 | zbc_val.color_l2[i] = 0; |
4223 | } | 4251 | } |
4224 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); | 4252 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); |
4225 | 4253 | ||
4226 | /* Opaque white (i.e. solid white) = (fmt 2 = uniform 1) */ | 4254 | /* Opaque white (i.e. solid white) = (fmt 2 = uniform 1) */ |
4227 | zbc_val.format = gr_ds_zbc_color_fmt_val_unorm_one_v(); | 4255 | zbc_val.format = gr_ds_zbc_color_fmt_val_unorm_one_v(); |
@@ -4244,11 +4272,11 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
4244 | 4272 | ||
4245 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); | 4273 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); |
4246 | zbc_val.depth = 0x3f800000; | 4274 | zbc_val.depth = 0x3f800000; |
4247 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); | 4275 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); |
4248 | 4276 | ||
4249 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); | 4277 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); |
4250 | zbc_val.depth = 0; | 4278 | zbc_val.depth = 0; |
4251 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); | 4279 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); |
4252 | 4280 | ||
4253 | if (!err) | 4281 | if (!err) |
4254 | gr->max_default_depth_index = 2; | 4282 | gr->max_default_depth_index = 2; |
@@ -4258,6 +4286,12 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
4258 | return err; | 4286 | return err; |
4259 | } | 4287 | } |
4260 | 4288 | ||
4289 | if (g->ops.gr.load_zbc_s_default_tbl) { | ||
4290 | err = g->ops.gr.load_zbc_s_default_tbl(g, gr); | ||
4291 | if (err) | ||
4292 | return err; | ||
4293 | } | ||
4294 | |||
4261 | return 0; | 4295 | return 0; |
4262 | } | 4296 | } |
4263 | 4297 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 33176df7..40b3bd44 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics Engine | 2 | * GK20A Graphics Engine |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -22,6 +22,10 @@ | |||
22 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 22 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC |
23 | #include "gr_t18x.h" | 23 | #include "gr_t18x.h" |
24 | #endif | 24 | #endif |
25 | #ifdef CONFIG_TEGRA_19x_GPU | ||
26 | #include "gr_t19x.h" | ||
27 | #endif | ||
28 | |||
25 | 29 | ||
26 | #include "tsg_gk20a.h" | 30 | #include "tsg_gk20a.h" |
27 | #include "gr_ctx_gk20a.h" | 31 | #include "gr_ctx_gk20a.h" |
@@ -141,6 +145,7 @@ struct gr_zcull_info { | |||
141 | #define GK20A_ZBC_TYPE_INVALID 0 | 145 | #define GK20A_ZBC_TYPE_INVALID 0 |
142 | #define GK20A_ZBC_TYPE_COLOR 1 | 146 | #define GK20A_ZBC_TYPE_COLOR 1 |
143 | #define GK20A_ZBC_TYPE_DEPTH 2 | 147 | #define GK20A_ZBC_TYPE_DEPTH 2 |
148 | #define T19X_ZBC 3 | ||
144 | 149 | ||
145 | struct zbc_color_table { | 150 | struct zbc_color_table { |
146 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; | 151 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; |
@@ -330,12 +335,20 @@ struct gr_gk20a { | |||
330 | struct mutex zbc_lock; | 335 | struct mutex zbc_lock; |
331 | struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; | 336 | struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; |
332 | struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; | 337 | struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; |
333 | 338 | #ifdef CONFIG_TEGRA_19x_GPU | |
339 | struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE]; | ||
340 | #endif | ||
334 | s32 max_default_color_index; | 341 | s32 max_default_color_index; |
335 | s32 max_default_depth_index; | 342 | s32 max_default_depth_index; |
343 | #ifdef CONFIG_TEGRA_19x_GPU | ||
344 | s32 max_default_s_index; | ||
345 | #endif | ||
336 | 346 | ||
337 | u32 max_used_color_index; | 347 | u32 max_used_color_index; |
338 | u32 max_used_depth_index; | 348 | u32 max_used_depth_index; |
349 | #ifdef CONFIG_TEGRA_19x_GPU | ||
350 | u32 max_used_s_index; | ||
351 | #endif | ||
339 | 352 | ||
340 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ | 353 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ |
341 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; | 354 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; |