gpu: nvgpu: gv11b: disable cbm alpha/beta cache invalidates

Disabled CBM alpha and beta cache invalidates as required
by hw. Since these registers are context switched out, added
these invalidates as part of gr init sequence, so golden context
restore these settings for all contexts.

Bug 2040262

Change-Id: Iffdd03f2ac6440ddd615899c407cfee692460918
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1648948
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Tested-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 36 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 61529a01..857f4944 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2711,6 +2711,14 @@ int gr_gv11b_init_fs_state(struct gk20a *g)
                         gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f());
         gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data);
 
+        /* Disable CBM alpha and beta invalidations for l2 */
+        data = gk20a_readl(g, gr_gpcs_ppcs_cbm_debug_r());
+        data = set_field(data, gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(),
+                        gr_gpcs_ppcs_cbm_debug_invalidate_alpha_disable_f());
+        data = set_field(data, gr_gpcs_ppcs_cbm_debug_invalidate_beta_m(),
+                        gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f());
+        gk20a_writel(g, gr_gpcs_ppcs_cbm_debug_r(), data);
+
         data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r());
         data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(),
                          gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 72cbc7dd..f40c7585 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -3636,6 +3636,34 @@ static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
 {
         return (v & 0xfffU) << 0U;
 }
+static inline u32 gr_gpcs_ppcs_cbm_debug_r(void)
+{
+        return 0x0041bec4U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_enable_f(void)
+{
+        return 0x2U;
+}
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
 {
         return 0x00418ea0U + i*4U;