diff options
author | Sunny He <suhe@nvidia.com> | 2017-07-31 21:54:38 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-11 17:16:52 -0400 |
commit | 8d63cd3995d4a650b478ad69d7e29ed2b1b2d927 (patch) | |
tree | 5acb73abbe5ef0b94d7147156fa23d707d6ed1c0 /drivers/gpu/nvgpu | |
parent | 63b74d4b768e0c96367d4983fdd8f1db1d317d01 (diff) |
gpu: nvgpu: Reorg mm HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I289284e6e528fc7951c959c8765ccf9349eec33b
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533351
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/mm_gp106.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/mm_gp106.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 19 |
12 files changed, 142 insertions, 88 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c index 36ca850e..71081be5 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c | |||
@@ -662,7 +662,7 @@ void gk20a_tegra_idle(struct device *dev) | |||
662 | 662 | ||
663 | void gk20a_tegra_init_secure_alloc(struct gk20a *g) | 663 | void gk20a_tegra_init_secure_alloc(struct gk20a *g) |
664 | { | 664 | { |
665 | g->ops.mm.secure_alloc = gk20a_tegra_secure_alloc; | 665 | g->ops.secure_alloc = gk20a_tegra_secure_alloc; |
666 | } | 666 | } |
667 | 667 | ||
668 | #ifdef CONFIG_COMMON_CLK | 668 | #ifdef CONFIG_COMMON_CLK |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 7b998204..58558159 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -734,16 +734,17 @@ struct gpu_ops { | |||
734 | void (*init_inst_block)(struct nvgpu_mem *inst_block, | 734 | void (*init_inst_block)(struct nvgpu_mem *inst_block, |
735 | struct vm_gk20a *vm, u32 big_page_size); | 735 | struct vm_gk20a *vm, u32 big_page_size); |
736 | bool (*mmu_fault_pending)(struct gk20a *g); | 736 | bool (*mmu_fault_pending)(struct gk20a *g); |
737 | /* This function is called to allocate secure memory (memory | ||
738 | * that the CPU cannot see). The function should fill the | ||
739 | * context buffer descriptor (especially fields destroy, sgt, | ||
740 | * size). | ||
741 | */ | ||
742 | int (*secure_alloc)(struct gk20a *g, | ||
743 | struct gr_ctx_buffer_desc *desc, | ||
744 | size_t size); | ||
745 | void (*fault_info_mem_destroy)(struct gk20a *g); | 737 | void (*fault_info_mem_destroy)(struct gk20a *g); |
746 | } mm; | 738 | } mm; |
739 | /* | ||
740 | * This function is called to allocate secure memory (memory | ||
741 | * that the CPU cannot see). The function should fill the | ||
742 | * context buffer descriptor (especially fields destroy, sgt, | ||
743 | * size). | ||
744 | */ | ||
745 | int (*secure_alloc)(struct gk20a *g, | ||
746 | struct gr_ctx_buffer_desc *desc, | ||
747 | size_t size); | ||
747 | struct { | 748 | struct { |
748 | u32 (*enter)(struct gk20a *g, struct nvgpu_mem *mem, | 749 | u32 (*enter)(struct gk20a *g, struct nvgpu_mem *mem, |
749 | struct page_alloc_chunk *chunk, u32 w); | 750 | struct page_alloc_chunk *chunk, u32 w); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 497e7ee2..608b011a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -2524,8 +2524,8 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) | |||
2524 | if (err) | 2524 | if (err) |
2525 | goto clean_up; | 2525 | goto clean_up; |
2526 | 2526 | ||
2527 | if (g->ops.mm.secure_alloc) | 2527 | if (g->ops.secure_alloc) |
2528 | g->ops.mm.secure_alloc(g, | 2528 | g->ops.secure_alloc(g, |
2529 | &gr->global_ctx_buffer[CIRCULAR_VPR], | 2529 | &gr->global_ctx_buffer[CIRCULAR_VPR], |
2530 | cb_buffer_size); | 2530 | cb_buffer_size); |
2531 | 2531 | ||
@@ -2536,8 +2536,8 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) | |||
2536 | if (err) | 2536 | if (err) |
2537 | goto clean_up; | 2537 | goto clean_up; |
2538 | 2538 | ||
2539 | if (g->ops.mm.secure_alloc) | 2539 | if (g->ops.secure_alloc) |
2540 | g->ops.mm.secure_alloc(g, | 2540 | g->ops.secure_alloc(g, |
2541 | &gr->global_ctx_buffer[PAGEPOOL_VPR], | 2541 | &gr->global_ctx_buffer[PAGEPOOL_VPR], |
2542 | pagepool_buffer_size); | 2542 | pagepool_buffer_size); |
2543 | 2543 | ||
@@ -2548,8 +2548,8 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) | |||
2548 | if (err) | 2548 | if (err) |
2549 | goto clean_up; | 2549 | goto clean_up; |
2550 | 2550 | ||
2551 | if (g->ops.mm.secure_alloc) | 2551 | if (g->ops.secure_alloc) |
2552 | g->ops.mm.secure_alloc(g, | 2552 | g->ops.secure_alloc(g, |
2553 | &gr->global_ctx_buffer[ATTRIBUTE_VPR], | 2553 | &gr->global_ctx_buffer[ATTRIBUTE_VPR], |
2554 | attr_buffer_size); | 2554 | attr_buffer_size); |
2555 | 2555 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index a540de64..1fb5b2bc 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include "gk20a/fb_gk20a.h" | 19 | #include "gk20a/fb_gk20a.h" |
20 | #include "gk20a/fifo_gk20a.h" | 20 | #include "gk20a/fifo_gk20a.h" |
21 | #include "gk20a/therm_gk20a.h" | 21 | #include "gk20a/therm_gk20a.h" |
22 | #include "gk20a/mm_gk20a.h" | ||
22 | #include "gk20a/css_gr_gk20a.h" | 23 | #include "gk20a/css_gr_gk20a.h" |
23 | #include "gk20a/mc_gk20a.h" | 24 | #include "gk20a/mc_gk20a.h" |
24 | #include "gk20a/bus_gk20a.h" | 25 | #include "gk20a/bus_gk20a.h" |
@@ -42,6 +43,8 @@ | |||
42 | #include "bus_gm20b.h" | 43 | #include "bus_gm20b.h" |
43 | #include "hal_gm20b.h" | 44 | #include "hal_gm20b.h" |
44 | 45 | ||
46 | #include "common/linux/platform_gk20a_tegra.h" | ||
47 | |||
45 | #include <nvgpu/debug.h> | 48 | #include <nvgpu/debug.h> |
46 | #include <nvgpu/bug.h> | 49 | #include <nvgpu/bug.h> |
47 | #include <nvgpu/enabled.h> | 50 | #include <nvgpu/enabled.h> |
@@ -287,6 +290,27 @@ static const struct gpu_ops gm20b_ops = { | |||
287 | .get_netlist_name = gr_gm20b_get_netlist_name, | 290 | .get_netlist_name = gr_gm20b_get_netlist_name, |
288 | .is_fw_defined = gr_gm20b_is_firmware_defined, | 291 | .is_fw_defined = gr_gm20b_is_firmware_defined, |
289 | }, | 292 | }, |
293 | .mm = { | ||
294 | .support_sparse = gm20b_mm_support_sparse, | ||
295 | .gmmu_map = gk20a_locked_gmmu_map, | ||
296 | .gmmu_unmap = gk20a_locked_gmmu_unmap, | ||
297 | .vm_bind_channel = gk20a_vm_bind_channel, | ||
298 | .fb_flush = gk20a_mm_fb_flush, | ||
299 | .l2_invalidate = gk20a_mm_l2_invalidate, | ||
300 | .l2_flush = gk20a_mm_l2_flush, | ||
301 | .cbc_clean = gk20a_mm_cbc_clean, | ||
302 | .set_big_page_size = gm20b_mm_set_big_page_size, | ||
303 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | ||
304 | .get_default_big_page_size = gm20b_mm_get_default_big_page_size, | ||
305 | .gpu_phys_addr = gm20b_gpu_phys_addr, | ||
306 | .get_physical_addr_bits = gk20a_mm_get_physical_addr_bits, | ||
307 | .get_mmu_levels = gk20a_mm_get_mmu_levels, | ||
308 | .init_pdb = gk20a_mm_init_pdb, | ||
309 | .init_mm_setup_hw = gk20a_init_mm_setup_hw, | ||
310 | .is_bar1_supported = gm20b_mm_is_bar1_supported, | ||
311 | .init_inst_block = gk20a_init_inst_block, | ||
312 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | ||
313 | }, | ||
290 | .therm = { | 314 | .therm = { |
291 | .init_therm_setup_hw = gm20b_init_therm_setup_hw, | 315 | .init_therm_setup_hw = gm20b_init_therm_setup_hw, |
292 | .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, | 316 | .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, |
@@ -398,6 +422,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
398 | gops->clock_gating = gm20b_ops.clock_gating; | 422 | gops->clock_gating = gm20b_ops.clock_gating; |
399 | gops->fifo = gm20b_ops.fifo; | 423 | gops->fifo = gm20b_ops.fifo; |
400 | gops->gr_ctx = gm20b_ops.gr_ctx; | 424 | gops->gr_ctx = gm20b_ops.gr_ctx; |
425 | gops->mm = gm20b_ops.mm; | ||
401 | gops->therm = gm20b_ops.therm; | 426 | gops->therm = gm20b_ops.therm; |
402 | /* | 427 | /* |
403 | * clk must be assigned member by member | 428 | * clk must be assigned member by member |
@@ -462,7 +487,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
462 | #endif | 487 | #endif |
463 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 488 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
464 | gm20b_init_gr(g); | 489 | gm20b_init_gr(g); |
465 | gm20b_init_mm(gops); | ||
466 | gm20b_init_pmu_ops(g); | 490 | gm20b_init_pmu_ops(g); |
467 | 491 | ||
468 | gm20b_init_uncompressed_kind_map(); | 492 | gm20b_init_uncompressed_kind_map(); |
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index bbcd6314..05752f03 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c | |||
@@ -20,7 +20,7 @@ | |||
20 | #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> | 20 | #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> |
21 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> | 21 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> |
22 | 22 | ||
23 | static void gm20b_mm_set_big_page_size(struct gk20a *g, | 23 | void gm20b_mm_set_big_page_size(struct gk20a *g, |
24 | struct nvgpu_mem *mem, int size) | 24 | struct nvgpu_mem *mem, int size) |
25 | { | 25 | { |
26 | u32 val; | 26 | u32 val; |
@@ -40,22 +40,22 @@ static void gm20b_mm_set_big_page_size(struct gk20a *g, | |||
40 | gk20a_dbg_fn("done"); | 40 | gk20a_dbg_fn("done"); |
41 | } | 41 | } |
42 | 42 | ||
43 | static u32 gm20b_mm_get_big_page_sizes(void) | 43 | u32 gm20b_mm_get_big_page_sizes(void) |
44 | { | 44 | { |
45 | return SZ_64K | SZ_128K; | 45 | return SZ_64K | SZ_128K; |
46 | } | 46 | } |
47 | 47 | ||
48 | static u32 gm20b_mm_get_default_big_page_size(void) | 48 | u32 gm20b_mm_get_default_big_page_size(void) |
49 | { | 49 | { |
50 | return SZ_128K; | 50 | return SZ_128K; |
51 | } | 51 | } |
52 | 52 | ||
53 | static bool gm20b_mm_support_sparse(struct gk20a *g) | 53 | bool gm20b_mm_support_sparse(struct gk20a *g) |
54 | { | 54 | { |
55 | return true; | 55 | return true; |
56 | } | 56 | } |
57 | 57 | ||
58 | static bool gm20b_mm_is_bar1_supported(struct gk20a *g) | 58 | bool gm20b_mm_is_bar1_supported(struct gk20a *g) |
59 | { | 59 | { |
60 | return true; | 60 | return true; |
61 | } | 61 | } |
@@ -65,26 +65,3 @@ u64 gm20b_gpu_phys_addr(struct gk20a *g, | |||
65 | { | 65 | { |
66 | return phys; | 66 | return phys; |
67 | } | 67 | } |
68 | |||
69 | void gm20b_init_mm(struct gpu_ops *gops) | ||
70 | { | ||
71 | gops->mm.support_sparse = gm20b_mm_support_sparse; | ||
72 | gops->mm.gmmu_map = gk20a_locked_gmmu_map; | ||
73 | gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; | ||
74 | gops->mm.vm_bind_channel = gk20a_vm_bind_channel; | ||
75 | gops->mm.fb_flush = gk20a_mm_fb_flush; | ||
76 | gops->mm.l2_invalidate = gk20a_mm_l2_invalidate; | ||
77 | gops->mm.l2_flush = gk20a_mm_l2_flush; | ||
78 | gops->mm.cbc_clean = gk20a_mm_cbc_clean; | ||
79 | gops->mm.set_big_page_size = gm20b_mm_set_big_page_size; | ||
80 | gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes; | ||
81 | gops->mm.get_default_big_page_size = gm20b_mm_get_default_big_page_size; | ||
82 | gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr; | ||
83 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; | ||
84 | gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; | ||
85 | gops->mm.init_pdb = gk20a_mm_init_pdb; | ||
86 | gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; | ||
87 | gops->mm.is_bar1_supported = gm20b_mm_is_bar1_supported; | ||
88 | gops->mm.init_inst_block = gk20a_init_inst_block; | ||
89 | gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending; | ||
90 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h index 2bb29ea8..b1bb38a3 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GMMU | 2 | * GM20B GMMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -20,9 +20,13 @@ struct gk20a; | |||
20 | #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) | 20 | #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) |
21 | #define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1)) | 21 | #define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1)) |
22 | 22 | ||
23 | void gm20b_mm_set_big_page_size(struct gk20a *g, | ||
24 | struct nvgpu_mem *mem, int size); | ||
25 | u32 gm20b_mm_get_big_page_sizes(void); | ||
26 | u32 gm20b_mm_get_default_big_page_size(void); | ||
27 | bool gm20b_mm_support_sparse(struct gk20a *g); | ||
28 | bool gm20b_mm_is_bar1_supported(struct gk20a *g); | ||
29 | int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g); | ||
23 | u64 gm20b_gpu_phys_addr(struct gk20a *g, | 30 | u64 gm20b_gpu_phys_addr(struct gk20a *g, |
24 | struct nvgpu_gmmu_attrs *attrs, u64 phys); | 31 | struct nvgpu_gmmu_attrs *attrs, u64 phys); |
25 | |||
26 | void gm20b_init_mm(struct gpu_ops *gops); | ||
27 | int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g); | ||
28 | #endif | 32 | #endif |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 361a7b0f..c919143c 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -17,6 +17,7 @@ | |||
17 | #include "gk20a/fifo_gk20a.h" | 17 | #include "gk20a/fifo_gk20a.h" |
18 | #include "gk20a/ctxsw_trace_gk20a.h" | 18 | #include "gk20a/ctxsw_trace_gk20a.h" |
19 | #include "gk20a/fecs_trace_gk20a.h" | 19 | #include "gk20a/fecs_trace_gk20a.h" |
20 | #include "gk20a/mm_gk20a.h" | ||
20 | #include "gk20a/dbg_gpu_gk20a.h" | 21 | #include "gk20a/dbg_gpu_gk20a.h" |
21 | #include "gk20a/css_gr_gk20a.h" | 22 | #include "gk20a/css_gr_gk20a.h" |
22 | #include "gk20a/bus_gk20a.h" | 23 | #include "gk20a/bus_gk20a.h" |
@@ -44,6 +45,7 @@ | |||
44 | #include "gm20b/ltc_gm20b.h" | 45 | #include "gm20b/ltc_gm20b.h" |
45 | #include "gm20b/gr_gm20b.h" | 46 | #include "gm20b/gr_gm20b.h" |
46 | #include "gm20b/fifo_gm20b.h" | 47 | #include "gm20b/fifo_gm20b.h" |
48 | #include "gm20b/mm_gm20b.h" | ||
47 | #include "gm20b/pmu_gm20b.h" | 49 | #include "gm20b/pmu_gm20b.h" |
48 | #include "gm20b/fb_gm20b.h" | 50 | #include "gm20b/fb_gm20b.h" |
49 | 51 | ||
@@ -65,6 +67,8 @@ | |||
65 | 67 | ||
66 | #include "hal_gp106.h" | 68 | #include "hal_gp106.h" |
67 | 69 | ||
70 | #include "common/linux/platform_gk20a_tegra.h" | ||
71 | |||
68 | #include <nvgpu/debug.h> | 72 | #include <nvgpu/debug.h> |
69 | #include <nvgpu/bug.h> | 73 | #include <nvgpu/bug.h> |
70 | #include <nvgpu/bus.h> | 74 | #include <nvgpu/bus.h> |
@@ -356,6 +360,31 @@ static const struct gpu_ops gp106_ops = { | |||
356 | .max_entries = gk20a_gr_max_entries, | 360 | .max_entries = gk20a_gr_max_entries, |
357 | }, | 361 | }, |
358 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ | 362 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ |
363 | .mm = { | ||
364 | .support_sparse = gm20b_mm_support_sparse, | ||
365 | .gmmu_map = gk20a_locked_gmmu_map, | ||
366 | .gmmu_unmap = gk20a_locked_gmmu_unmap, | ||
367 | .vm_bind_channel = gk20a_vm_bind_channel, | ||
368 | .fb_flush = gk20a_mm_fb_flush, | ||
369 | .l2_invalidate = gk20a_mm_l2_invalidate, | ||
370 | .l2_flush = gk20a_mm_l2_flush, | ||
371 | .cbc_clean = gk20a_mm_cbc_clean, | ||
372 | .set_big_page_size = gm20b_mm_set_big_page_size, | ||
373 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | ||
374 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | ||
375 | .gpu_phys_addr = gm20b_gpu_phys_addr, | ||
376 | .get_physical_addr_bits = NULL, | ||
377 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | ||
378 | .init_pdb = gp10b_mm_init_pdb, | ||
379 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, | ||
380 | .is_bar1_supported = gm20b_mm_is_bar1_supported, | ||
381 | .init_inst_block = gk20a_init_inst_block, | ||
382 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | ||
383 | .init_bar2_vm = gb10b_init_bar2_vm, | ||
384 | .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup, | ||
385 | .remove_bar2_vm = gp10b_remove_bar2_vm, | ||
386 | .get_vidmem_size = gp106_mm_get_vidmem_size, | ||
387 | }, | ||
359 | .pramin = { | 388 | .pramin = { |
360 | .enter = gk20a_pramin_enter, | 389 | .enter = gk20a_pramin_enter, |
361 | .exit = gk20a_pramin_exit, | 390 | .exit = gk20a_pramin_exit, |
@@ -502,6 +531,7 @@ int gp106_init_hal(struct gk20a *g) | |||
502 | gops->fifo = gp106_ops.fifo; | 531 | gops->fifo = gp106_ops.fifo; |
503 | gops->gr_ctx = gp106_ops.gr_ctx; | 532 | gops->gr_ctx = gp106_ops.gr_ctx; |
504 | gops->fecs_trace = gp106_ops.fecs_trace; | 533 | gops->fecs_trace = gp106_ops.fecs_trace; |
534 | gops->mm = gp106_ops.mm; | ||
505 | gops->pramin = gp106_ops.pramin; | 535 | gops->pramin = gp106_ops.pramin; |
506 | gops->therm = gp106_ops.therm; | 536 | gops->therm = gp106_ops.therm; |
507 | /* | 537 | /* |
@@ -543,7 +573,6 @@ int gp106_init_hal(struct gk20a *g) | |||
543 | 573 | ||
544 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 574 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
545 | gp106_init_gr(g); | 575 | gp106_init_gr(g); |
546 | gp106_init_mm(gops); | ||
547 | gp106_init_pmu_ops(g); | 576 | gp106_init_pmu_ops(g); |
548 | 577 | ||
549 | gp10b_init_uncompressed_kind_map(); | 578 | gp10b_init_uncompressed_kind_map(); |
diff --git a/drivers/gpu/nvgpu/gp106/mm_gp106.c b/drivers/gpu/nvgpu/gp106/mm_gp106.c index b7d7e8b8..82c58e97 100644 --- a/drivers/gpu/nvgpu/gp106/mm_gp106.c +++ b/drivers/gpu/nvgpu/gp106/mm_gp106.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP106 memory management | 2 | * GP106 memory management |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -19,7 +19,7 @@ | |||
19 | 19 | ||
20 | #include <nvgpu/hw/gp106/hw_fb_gp106.h> | 20 | #include <nvgpu/hw/gp106/hw_fb_gp106.h> |
21 | 21 | ||
22 | static size_t gp106_mm_get_vidmem_size(struct gk20a *g) | 22 | size_t gp106_mm_get_vidmem_size(struct gk20a *g) |
23 | { | 23 | { |
24 | u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); | 24 | u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); |
25 | u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); | 25 | u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); |
@@ -32,10 +32,3 @@ static size_t gp106_mm_get_vidmem_size(struct gk20a *g) | |||
32 | 32 | ||
33 | return bytes; | 33 | return bytes; |
34 | } | 34 | } |
35 | |||
36 | void gp106_init_mm(struct gpu_ops *gops) | ||
37 | { | ||
38 | gp10b_init_mm(gops); | ||
39 | gops->mm.get_vidmem_size = gp106_mm_get_vidmem_size; | ||
40 | gops->mm.get_physical_addr_bits = NULL; | ||
41 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/mm_gp106.h b/drivers/gpu/nvgpu/gp106/mm_gp106.h index 36a89a11..73b128a6 100644 --- a/drivers/gpu/nvgpu/gp106/mm_gp106.h +++ b/drivers/gpu/nvgpu/gp106/mm_gp106.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP106 memory management | 2 | * GP106 memory management |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -16,8 +16,8 @@ | |||
16 | #ifndef MM_GP106_H | 16 | #ifndef MM_GP106_H |
17 | #define MM_GP106_H | 17 | #define MM_GP106_H |
18 | 18 | ||
19 | struct gpu_ops; | 19 | struct gk20a; |
20 | 20 | ||
21 | void gp106_init_mm(struct gpu_ops *gops); | 21 | size_t gp106_mm_get_vidmem_size(struct gk20a *g); |
22 | 22 | ||
23 | #endif | 23 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index b0871155..a70565c3 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -17,6 +17,7 @@ | |||
17 | #include "gk20a/fifo_gk20a.h" | 17 | #include "gk20a/fifo_gk20a.h" |
18 | #include "gk20a/ctxsw_trace_gk20a.h" | 18 | #include "gk20a/ctxsw_trace_gk20a.h" |
19 | #include "gk20a/fecs_trace_gk20a.h" | 19 | #include "gk20a/fecs_trace_gk20a.h" |
20 | #include "gk20a/mm_gk20a.h" | ||
20 | #include "gk20a/dbg_gpu_gk20a.h" | 21 | #include "gk20a/dbg_gpu_gk20a.h" |
21 | #include "gk20a/css_gr_gk20a.h" | 22 | #include "gk20a/css_gr_gk20a.h" |
22 | #include "gk20a/bus_gk20a.h" | 23 | #include "gk20a/bus_gk20a.h" |
@@ -47,12 +48,14 @@ | |||
47 | #include "gm20b/fifo_gm20b.h" | 48 | #include "gm20b/fifo_gm20b.h" |
48 | #include "gm20b/pmu_gm20b.h" | 49 | #include "gm20b/pmu_gm20b.h" |
49 | #include "gm20b/clk_gm20b.h" | 50 | #include "gm20b/clk_gm20b.h" |
50 | #include "gm20b/fifo_gm20b.h" | ||
51 | #include "gm20b/fb_gm20b.h" | 51 | #include "gm20b/fb_gm20b.h" |
52 | #include "gm20b/mm_gm20b.h" | ||
52 | 53 | ||
53 | #include "gp10b.h" | 54 | #include "gp10b.h" |
54 | #include "hal_gp10b.h" | 55 | #include "hal_gp10b.h" |
55 | 56 | ||
57 | #include "common/linux/platform_gk20a_tegra.h" | ||
58 | |||
56 | #include <nvgpu/debug.h> | 59 | #include <nvgpu/debug.h> |
57 | #include <nvgpu/bug.h> | 60 | #include <nvgpu/bug.h> |
58 | #include <nvgpu/enabled.h> | 61 | #include <nvgpu/enabled.h> |
@@ -319,6 +322,30 @@ static const struct gpu_ops gp10b_ops = { | |||
319 | .max_entries = gk20a_gr_max_entries, | 322 | .max_entries = gk20a_gr_max_entries, |
320 | }, | 323 | }, |
321 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ | 324 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ |
325 | .mm = { | ||
326 | .support_sparse = gm20b_mm_support_sparse, | ||
327 | .gmmu_map = gk20a_locked_gmmu_map, | ||
328 | .gmmu_unmap = gk20a_locked_gmmu_unmap, | ||
329 | .vm_bind_channel = gk20a_vm_bind_channel, | ||
330 | .fb_flush = gk20a_mm_fb_flush, | ||
331 | .l2_invalidate = gk20a_mm_l2_invalidate, | ||
332 | .l2_flush = gk20a_mm_l2_flush, | ||
333 | .cbc_clean = gk20a_mm_cbc_clean, | ||
334 | .set_big_page_size = gm20b_mm_set_big_page_size, | ||
335 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | ||
336 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | ||
337 | .gpu_phys_addr = gm20b_gpu_phys_addr, | ||
338 | .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, | ||
339 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | ||
340 | .init_pdb = gp10b_mm_init_pdb, | ||
341 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, | ||
342 | .is_bar1_supported = gm20b_mm_is_bar1_supported, | ||
343 | .init_inst_block = gk20a_init_inst_block, | ||
344 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | ||
345 | .init_bar2_vm = gb10b_init_bar2_vm, | ||
346 | .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup, | ||
347 | .remove_bar2_vm = gp10b_remove_bar2_vm, | ||
348 | }, | ||
322 | .pramin = { | 349 | .pramin = { |
323 | .enter = gk20a_pramin_enter, | 350 | .enter = gk20a_pramin_enter, |
324 | .exit = gk20a_pramin_exit, | 351 | .exit = gk20a_pramin_exit, |
@@ -427,6 +454,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
427 | gops->fifo = gp10b_ops.fifo; | 454 | gops->fifo = gp10b_ops.fifo; |
428 | gops->gr_ctx = gp10b_ops.gr_ctx; | 455 | gops->gr_ctx = gp10b_ops.gr_ctx; |
429 | gops->fecs_trace = gp10b_ops.fecs_trace; | 456 | gops->fecs_trace = gp10b_ops.fecs_trace; |
457 | gops->mm = gp10b_ops.mm; | ||
430 | gops->pramin = gp10b_ops.pramin; | 458 | gops->pramin = gp10b_ops.pramin; |
431 | gops->therm = gp10b_ops.therm; | 459 | gops->therm = gp10b_ops.therm; |
432 | gops->regops = gp10b_ops.regops; | 460 | gops->regops = gp10b_ops.regops; |
@@ -489,7 +517,6 @@ int gp10b_init_hal(struct gk20a *g) | |||
489 | 517 | ||
490 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 518 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
491 | gp10b_init_gr(g); | 519 | gp10b_init_gr(g); |
492 | gp10b_init_mm(gops); | ||
493 | gp10b_init_pmu_ops(g); | 520 | gp10b_init_pmu_ops(g); |
494 | 521 | ||
495 | gp10b_init_uncompressed_kind_map(); | 522 | gp10b_init_uncompressed_kind_map(); |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 729ccc39..5c17244d 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -27,17 +27,17 @@ | |||
27 | #include <nvgpu/hw/gp10b/hw_bus_gp10b.h> | 27 | #include <nvgpu/hw/gp10b/hw_bus_gp10b.h> |
28 | #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h> | 28 | #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h> |
29 | 29 | ||
30 | static u32 gp10b_mm_get_default_big_page_size(void) | 30 | u32 gp10b_mm_get_default_big_page_size(void) |
31 | { | 31 | { |
32 | return SZ_64K; | 32 | return SZ_64K; |
33 | } | 33 | } |
34 | 34 | ||
35 | static u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) | 35 | u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) |
36 | { | 36 | { |
37 | return 36; | 37 | return 36; |
38 | } | 38 | } |
39 | 39 | ||
40 | static int gp10b_init_mm_setup_hw(struct gk20a *g) | 40 | int gp10b_init_mm_setup_hw(struct gk20a *g) |
41 | { | 41 | { |
42 | struct mm_gk20a *mm = &g->mm; | 42 | struct mm_gk20a *mm = &g->mm; |
43 | struct nvgpu_mem *inst_block = &mm->bar1.inst_block; | 43 | struct nvgpu_mem *inst_block = &mm->bar1.inst_block; |
@@ -68,7 +68,7 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g) | |||
68 | 68 | ||
69 | } | 69 | } |
70 | 70 | ||
71 | static int gb10b_init_bar2_vm(struct gk20a *g) | 71 | int gb10b_init_bar2_vm(struct gk20a *g) |
72 | { | 72 | { |
73 | int err; | 73 | int err; |
74 | struct mm_gk20a *mm = &g->mm; | 74 | struct mm_gk20a *mm = &g->mm; |
@@ -99,7 +99,7 @@ clean_up_va: | |||
99 | return err; | 99 | return err; |
100 | } | 100 | } |
101 | 101 | ||
102 | static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) | 102 | int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) |
103 | { | 103 | { |
104 | struct mm_gk20a *mm = &g->mm; | 104 | struct mm_gk20a *mm = &g->mm; |
105 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; | 105 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; |
@@ -333,13 +333,13 @@ static const struct gk20a_mmu_level gp10b_mm_levels[] = { | |||
333 | {.update_entry = NULL} | 333 | {.update_entry = NULL} |
334 | }; | 334 | }; |
335 | 335 | ||
336 | static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, | 336 | const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, |
337 | u32 big_page_size) | 337 | u32 big_page_size) |
338 | { | 338 | { |
339 | return gp10b_mm_levels; | 339 | return gp10b_mm_levels; |
340 | } | 340 | } |
341 | 341 | ||
342 | static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | 342 | void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, |
343 | struct vm_gk20a *vm) | 343 | struct vm_gk20a *vm) |
344 | { | 344 | { |
345 | u64 pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); | 345 | u64 pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); |
@@ -360,7 +360,7 @@ static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | |||
360 | ram_in_page_dir_base_hi_f(pdb_addr_hi)); | 360 | ram_in_page_dir_base_hi_f(pdb_addr_hi)); |
361 | } | 361 | } |
362 | 362 | ||
363 | static void gp10b_remove_bar2_vm(struct gk20a *g) | 363 | void gp10b_remove_bar2_vm(struct gk20a *g) |
364 | { | 364 | { |
365 | struct mm_gk20a *mm = &g->mm; | 365 | struct mm_gk20a *mm = &g->mm; |
366 | 366 | ||
@@ -368,17 +368,3 @@ static void gp10b_remove_bar2_vm(struct gk20a *g) | |||
368 | gk20a_free_inst_block(g, &mm->bar2.inst_block); | 368 | gk20a_free_inst_block(g, &mm->bar2.inst_block); |
369 | nvgpu_vm_put(mm->bar2.vm); | 369 | nvgpu_vm_put(mm->bar2.vm); |
370 | } | 370 | } |
371 | |||
372 | |||
373 | void gp10b_init_mm(struct gpu_ops *gops) | ||
374 | { | ||
375 | gm20b_init_mm(gops); | ||
376 | gops->mm.get_default_big_page_size = gp10b_mm_get_default_big_page_size; | ||
377 | gops->mm.get_physical_addr_bits = gp10b_mm_get_physical_addr_bits; | ||
378 | gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw; | ||
379 | gops->mm.init_bar2_vm = gb10b_init_bar2_vm; | ||
380 | gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; | ||
381 | gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels; | ||
382 | gops->mm.init_pdb = gp10b_mm_init_pdb; | ||
383 | gops->mm.remove_bar2_vm = gp10b_remove_bar2_vm; | ||
384 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index 4cc71ea6..a0b9acd6 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -14,7 +14,20 @@ | |||
14 | #ifndef MM_GP10B_H | 14 | #ifndef MM_GP10B_H |
15 | #define MM_GP10B_H | 15 | #define MM_GP10B_H |
16 | 16 | ||
17 | struct gpu_ops; | 17 | struct gk20a; |
18 | struct gk20a_mmu_level; | ||
19 | struct nvgpu_mem; | ||
20 | struct vm_gk20a; | ||
21 | |||
22 | u32 gp10b_mm_get_default_big_page_size(void); | ||
23 | u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g); | ||
24 | int gp10b_init_mm_setup_hw(struct gk20a *g); | ||
25 | int gb10b_init_bar2_vm(struct gk20a *g); | ||
26 | int gb10b_init_bar2_mm_hw_setup(struct gk20a *g); | ||
27 | const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, | ||
28 | u32 big_page_size); | ||
29 | void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | ||
30 | struct vm_gk20a *vm); | ||
31 | void gp10b_remove_bar2_vm(struct gk20a *g); | ||
18 | 32 | ||
19 | void gp10b_init_mm(struct gpu_ops *gops); | ||
20 | #endif | 33 | #endif |