gpu: nvgpu: get ctx id from valid ctx mem

ctx id should be read from right mem area else
it will return 0 and cause issue with fecs methods
that depend on ctx id

Bug 200289491

Change-Id: Iba74f653afccf34e95cd90175833e3270239c264
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1505902
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 12 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index f101d3ba..4219e841 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -102,18 +102,27 @@ int gr_gk20a_get_ctx_id(struct gk20a *g,
                 u32 *ctx_id)
 {
         struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
+        struct ctx_header_desc *ctx_header = &ch_ctx->ctx_header;
+        struct nvgpu_mem *ctx_header_mem = &ctx_header->mem;
+        struct nvgpu_mem *mem;
 
         /* Channel gr_ctx buffer is gpu cacheable.
            Flush and invalidate before cpu update. */
         g->ops.mm.l2_flush(g, true);
 
-        if (nvgpu_mem_begin(g, &ch_ctx->gr_ctx->mem))
+        if (ctx_header_mem->gpu_va)
+                mem = ctx_header_mem;
+        else
+                mem = &ch_ctx->gr_ctx->mem;
+
+        if (nvgpu_mem_begin(g, mem))
                 return -ENOMEM;
 
-        *ctx_id = nvgpu_mem_rd(g, &ch_ctx->gr_ctx->mem,
+        *ctx_id = nvgpu_mem_rd(g, mem,
                         ctxsw_prog_main_image_context_id_o());
+        gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, "ctx_id: 0x%x", *ctx_id);
 
-        nvgpu_mem_end(g, &ch_ctx->gr_ctx->mem);
+        nvgpu_mem_end(g, mem);
 
         return 0;
 }