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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-04-19 17:09:05 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-27 06:57:13 -0400
commit8b3d94ffd3e5b6d7a622c6ad54692d79bf39d1ce (patch)
treefb8648cd40e99892e18e28de8e8851915a0ac0b9 /drivers/gpu/nvgpu
parent52445fba1feac3ee20bf1c3db149adc42715af9e (diff)
gpu: nvgpu: Move sysfs dependencies from HAL to Linux
Move sysfs dependencies from gk20a/ and gp10b/ to common/linux. At the same time the gk20a and gp10b variants are merged into one. JIRA NVGPU-48 Change-Id: I212be8f1beb8d20a57de04a57513e8fa0e2e83b4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1466055 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/Makefile.nvgpu3
-rw-r--r--drivers/gpu/nvgpu/common/linux/driver_common.c3
-rw-r--r--drivers/gpu/nvgpu/common/linux/module.c4
-rw-r--r--drivers/gpu/nvgpu/common/linux/pci.c4
-rw-r--r--drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c6
-rw-r--r--drivers/gpu/nvgpu/common/linux/sysfs.c (renamed from drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c)148
-rw-r--r--drivers/gpu/nvgpu/common/linux/sysfs.h (renamed from drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h)18
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h3
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c68
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c3
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.c1
11 files changed, 117 insertions, 144 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu
index 6dbba4d9..6ffbdc44 100644
--- a/drivers/gpu/nvgpu/Makefile.nvgpu
+++ b/drivers/gpu/nvgpu/Makefile.nvgpu
@@ -43,6 +43,7 @@ nvgpu-y := \
43 common/linux/thread.o \ 43 common/linux/thread.o \
44 common/linux/vm.o \ 44 common/linux/vm.o \
45 common/linux/intr.o \ 45 common/linux/intr.o \
46 common/linux/sysfs.o \
46 common/mm/nvgpu_allocator.o \ 47 common/mm/nvgpu_allocator.o \
47 common/mm/bitmap_allocator.o \ 48 common/mm/bitmap_allocator.o \
48 common/mm/buddy_allocator.o \ 49 common/mm/buddy_allocator.o \
@@ -85,7 +86,6 @@ nvgpu-y := \
85 gk20a/gr_ctx_gk20a_sim.o \ 86 gk20a/gr_ctx_gk20a_sim.o \
86 gk20a/gr_ctx_gk20a.o \ 87 gk20a/gr_ctx_gk20a.o \
87 gk20a/gk20a_gating_reglist.o \ 88 gk20a/gk20a_gating_reglist.o \
88 gk20a/gk20a_sysfs.o \
89 gk20a/ltc_gk20a.o \ 89 gk20a/ltc_gk20a.o \
90 gk20a/fb_gk20a.o \ 90 gk20a/fb_gk20a.o \
91 gk20a/hal.o \ 91 gk20a/hal.o \
@@ -186,7 +186,6 @@ nvgpu-y += \
186 gp10b/cde_gp10b.o \ 186 gp10b/cde_gp10b.o \
187 gp10b/therm_gp10b.o \ 187 gp10b/therm_gp10b.o \
188 gp10b/fecs_trace_gp10b.o \ 188 gp10b/fecs_trace_gp10b.o \
189 gp10b/gp10b_sysfs.o \
190 gp10b/priv_ring_gp10b.o \ 189 gp10b/priv_ring_gp10b.o \
191 gp10b/gp10b.o \ 190 gp10b/gp10b.o \
192 gp106/hal_gp106.o \ 191 gp106/hal_gp106.o \
diff --git a/drivers/gpu/nvgpu/common/linux/driver_common.c b/drivers/gpu/nvgpu/common/linux/driver_common.c
index c4d40c35..a7bc230c 100644
--- a/drivers/gpu/nvgpu/common/linux/driver_common.c
+++ b/drivers/gpu/nvgpu/common/linux/driver_common.c
@@ -28,6 +28,7 @@
28#include "gk20a/platform_gk20a.h" 28#include "gk20a/platform_gk20a.h"
29#include "module.h" 29#include "module.h"
30#include "os_linux.h" 30#include "os_linux.h"
31#include "sysfs.h"
31 32
32#define EMC3D_DEFAULT_RATIO 750 33#define EMC3D_DEFAULT_RATIO 750
33 34
@@ -190,7 +191,7 @@ int nvgpu_probe(struct gk20a *g,
190 191
191 nvgpu_init_mm_vars(g); 192 nvgpu_init_mm_vars(g);
192 193
193 gk20a_create_sysfs(g->dev); 194 nvgpu_create_sysfs(g->dev);
194 gk20a_debug_init(g, debugfs_symlink); 195 gk20a_debug_init(g, debugfs_symlink);
195 196
196 g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K); 197 g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K);
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c
index bfd2c790..99bbc25e 100644
--- a/drivers/gpu/nvgpu/common/linux/module.c
+++ b/drivers/gpu/nvgpu/common/linux/module.c
@@ -31,8 +31,8 @@
31#include <nvgpu/enabled.h> 31#include <nvgpu/enabled.h>
32#include <nvgpu/debug.h> 32#include <nvgpu/debug.h>
33 33
34#include "gk20a/gk20a.h"
35#include "gk20a/platform_gk20a.h" 34#include "gk20a/platform_gk20a.h"
35#include "sysfs.h"
36#include "vgpu/vgpu.h" 36#include "vgpu/vgpu.h"
37#include "gk20a/gk20a_scale.h" 37#include "gk20a/gk20a_scale.h"
38#include "gk20a/ctxsw_trace_gk20a.h" 38#include "gk20a/ctxsw_trace_gk20a.h"
@@ -985,7 +985,7 @@ static int __exit gk20a_remove(struct platform_device *pdev)
985 985
986 gk20a_debug_deinit(g); 986 gk20a_debug_deinit(g);
987 987
988 gk20a_remove_sysfs(dev); 988 nvgpu_remove_sysfs(dev);
989 989
990 if (platform->secure_buffer.destroy) 990 if (platform->secure_buffer.destroy)
991 platform->secure_buffer.destroy(g, 991 platform->secure_buffer.destroy(g,
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c
index cb315973..acb1bb9f 100644
--- a/drivers/gpu/nvgpu/common/linux/pci.c
+++ b/drivers/gpu/nvgpu/common/linux/pci.c
@@ -29,7 +29,7 @@
29#include "module.h" 29#include "module.h"
30#include "intr.h" 30#include "intr.h"
31#include "gp106/pmu_mclk_gp106.h" 31#include "gp106/pmu_mclk_gp106.h"
32 32#include "sysfs.h"
33#include "pci.h" 33#include "pci.h"
34 34
35#include "os_linux.h" 35#include "os_linux.h"
@@ -491,7 +491,7 @@ static void nvgpu_pci_remove(struct pci_dev *pdev)
491 debugfs_remove_recursive(platform->debugfs_alias); 491 debugfs_remove_recursive(platform->debugfs_alias);
492#endif 492#endif
493 493
494 gk20a_remove_sysfs(g->dev); 494 nvgpu_remove_sysfs(g->dev);
495 495
496 if (platform->remove) 496 if (platform->remove)
497 platform->remove(g->dev); 497 platform->remove(g->dev);
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
index 5980c592..ab2aa1c5 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
+++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
@@ -38,7 +38,6 @@
38#include "gk20a/gk20a_scale.h" 38#include "gk20a/gk20a_scale.h"
39 39
40#include "platform_gk20a_tegra.h" 40#include "platform_gk20a_tegra.h"
41#include "gp10b/gp10b_sysfs.h"
42#include "gp10b/platform_gp10b.h" 41#include "gp10b/platform_gp10b.h"
43#include "platform_gp10b_tegra.h" 42#include "platform_gp10b_tegra.h"
44 43
@@ -161,9 +160,6 @@ static int gp10b_tegra_late_probe(struct device *dev)
161 /* Cause early VPR resize */ 160 /* Cause early VPR resize */
162 gk20a_tegra_secure_page_alloc(dev); 161 gk20a_tegra_secure_page_alloc(dev);
163 162
164 /*Create GP10B specific sysfs*/
165 gp10b_create_sysfs(dev);
166
167 /* Initialise tegra specific scaling quirks */ 163 /* Initialise tegra specific scaling quirks */
168 gp10b_tegra_scale_init(dev); 164 gp10b_tegra_scale_init(dev);
169 return 0; 165 return 0;
@@ -172,8 +168,6 @@ static int gp10b_tegra_late_probe(struct device *dev)
172int gp10b_tegra_remove(struct device *dev) 168int gp10b_tegra_remove(struct device *dev)
173{ 169{
174 gr_gp10b_remove_sysfs(dev); 170 gr_gp10b_remove_sysfs(dev);
175 /*Remove GP10B specific sysfs*/
176 gp10b_remove_sysfs(dev);
177 171
178 /* deinitialise tegra specific scaling quirks */ 172 /* deinitialise tegra specific scaling quirks */
179 gp10b_tegra_scale_exit(dev); 173 gp10b_tegra_scale_exit(dev);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c b/drivers/gpu/nvgpu/common/linux/sysfs.c
index 1933eed5..e0da4661 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
+++ b/drivers/gpu/nvgpu/common/linux/sysfs.c
@@ -1,8 +1,4 @@
1/* 1/*
2 * drivers/video/tegra/host/gk20a/gk20a_sysfs.c
3 *
4 * GK20A Graphics
5 *
6 * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
7 * 3 *
8 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
@@ -22,18 +18,15 @@
22#include <linux/device.h> 18#include <linux/device.h>
23#include <linux/pm_runtime.h> 19#include <linux/pm_runtime.h>
24#include <linux/fb.h> 20#include <linux/fb.h>
25#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
26#include <soc/tegra/tegra-dvfs.h> 21#include <soc/tegra/tegra-dvfs.h>
27#endif
28 22
29#include <nvgpu/kmem.h> 23#include <nvgpu/kmem.h>
30#include <nvgpu/nvhost.h> 24#include <nvgpu/nvhost.h>
31 25
32#include "gk20a.h" 26#include "sysfs.h"
33#include "gk20a/platform_gk20a.h" 27#include "gk20a/platform_gk20a.h"
34#include "gr_gk20a.h" 28#include "gk20a/pmu_gk20a.h"
35#include "fifo_gk20a.h" 29#include "gk20a/gr_gk20a.h"
36#include "pmu_gk20a.h"
37 30
38#define PTIMER_FP_FACTOR 1000000 31#define PTIMER_FP_FACTOR 1000000
39 32
@@ -63,7 +56,7 @@ static ssize_t elcg_enable_store(struct device *dev,
63 56
64 gk20a_idle(g); 57 gk20a_idle(g);
65 58
66 dev_info(dev, "ELCG is %s.\n", g->elcg_enabled ? "enabled" : 59 nvgpu_info(g, "ELCG is %s.", g->elcg_enabled ? "enabled" :
67 "disabled"); 60 "disabled");
68 61
69 return count; 62 return count;
@@ -99,28 +92,35 @@ static ssize_t blcg_enable_store(struct device *dev,
99 return err; 92 return err;
100 93
101 if (g->ops.clock_gating.blcg_bus_load_gating_prod) 94 if (g->ops.clock_gating.blcg_bus_load_gating_prod)
102 g->ops.clock_gating.blcg_bus_load_gating_prod(g, g->blcg_enabled); 95 g->ops.clock_gating.blcg_bus_load_gating_prod(g,
96 g->blcg_enabled);
103 if (g->ops.clock_gating.blcg_ce_load_gating_prod) 97 if (g->ops.clock_gating.blcg_ce_load_gating_prod)
104 g->ops.clock_gating.blcg_ce_load_gating_prod(g, 98 g->ops.clock_gating.blcg_ce_load_gating_prod(g,
105 g->blcg_enabled); 99 g->blcg_enabled);
106 if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod) 100 if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod)
107 g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g, g->blcg_enabled); 101 g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g,
102 g->blcg_enabled);
108 if (g->ops.clock_gating.blcg_fb_load_gating_prod) 103 if (g->ops.clock_gating.blcg_fb_load_gating_prod)
109 g->ops.clock_gating.blcg_fb_load_gating_prod(g, g->blcg_enabled); 104 g->ops.clock_gating.blcg_fb_load_gating_prod(g,
105 g->blcg_enabled);
110 if (g->ops.clock_gating.blcg_fifo_load_gating_prod) 106 if (g->ops.clock_gating.blcg_fifo_load_gating_prod)
111 g->ops.clock_gating.blcg_fifo_load_gating_prod(g, g->blcg_enabled); 107 g->ops.clock_gating.blcg_fifo_load_gating_prod(g,
108 g->blcg_enabled);
112 if (g->ops.clock_gating.blcg_gr_load_gating_prod) 109 if (g->ops.clock_gating.blcg_gr_load_gating_prod)
113 g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled); 110 g->ops.clock_gating.blcg_gr_load_gating_prod(g,
111 g->blcg_enabled);
114 if (g->ops.clock_gating.blcg_ltc_load_gating_prod) 112 if (g->ops.clock_gating.blcg_ltc_load_gating_prod)
115 g->ops.clock_gating.blcg_ltc_load_gating_prod(g, g->blcg_enabled); 113 g->ops.clock_gating.blcg_ltc_load_gating_prod(g,
114 g->blcg_enabled);
116 if (g->ops.clock_gating.blcg_pmu_load_gating_prod) 115 if (g->ops.clock_gating.blcg_pmu_load_gating_prod)
117 g->ops.clock_gating.blcg_pmu_load_gating_prod(g, g->blcg_enabled); 116 g->ops.clock_gating.blcg_pmu_load_gating_prod(g,
117 g->blcg_enabled);
118 if (g->ops.clock_gating.blcg_xbar_load_gating_prod) 118 if (g->ops.clock_gating.blcg_xbar_load_gating_prod)
119 g->ops.clock_gating.blcg_xbar_load_gating_prod(g, 119 g->ops.clock_gating.blcg_xbar_load_gating_prod(g,
120 g->blcg_enabled); 120 g->blcg_enabled);
121 gk20a_idle(g); 121 gk20a_idle(g);
122 122
123 dev_info(dev, "BLCG is %s.\n", g->blcg_enabled ? "enabled" : 123 nvgpu_info(g, "BLCG is %s.", g->blcg_enabled ? "enabled" :
124 "disabled"); 124 "disabled");
125 125
126 return count; 126 return count;
@@ -162,32 +162,44 @@ static ssize_t slcg_enable_store(struct device *dev,
162 return err; 162 return err;
163 163
164 if (g->ops.clock_gating.slcg_bus_load_gating_prod) 164 if (g->ops.clock_gating.slcg_bus_load_gating_prod)
165 g->ops.clock_gating.slcg_bus_load_gating_prod(g, g->slcg_enabled); 165 g->ops.clock_gating.slcg_bus_load_gating_prod(g,
166 g->slcg_enabled);
166 if (g->ops.clock_gating.slcg_ce2_load_gating_prod) 167 if (g->ops.clock_gating.slcg_ce2_load_gating_prod)
167 g->ops.clock_gating.slcg_ce2_load_gating_prod(g, g->slcg_enabled); 168 g->ops.clock_gating.slcg_ce2_load_gating_prod(g,
169 g->slcg_enabled);
168 if (g->ops.clock_gating.slcg_chiplet_load_gating_prod) 170 if (g->ops.clock_gating.slcg_chiplet_load_gating_prod)
169 g->ops.clock_gating.slcg_chiplet_load_gating_prod(g, g->slcg_enabled); 171 g->ops.clock_gating.slcg_chiplet_load_gating_prod(g,
172 g->slcg_enabled);
170 if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod) 173 if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod)
171 g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g, g->slcg_enabled); 174 g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g,
175 g->slcg_enabled);
172 if (g->ops.clock_gating.slcg_fb_load_gating_prod) 176 if (g->ops.clock_gating.slcg_fb_load_gating_prod)
173 g->ops.clock_gating.slcg_fb_load_gating_prod(g, g->slcg_enabled); 177 g->ops.clock_gating.slcg_fb_load_gating_prod(g,
178 g->slcg_enabled);
174 if (g->ops.clock_gating.slcg_fifo_load_gating_prod) 179 if (g->ops.clock_gating.slcg_fifo_load_gating_prod)
175 g->ops.clock_gating.slcg_fifo_load_gating_prod(g, g->slcg_enabled); 180 g->ops.clock_gating.slcg_fifo_load_gating_prod(g,
181 g->slcg_enabled);
176 if (g->ops.clock_gating.slcg_gr_load_gating_prod) 182 if (g->ops.clock_gating.slcg_gr_load_gating_prod)
177 g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled); 183 g->ops.clock_gating.slcg_gr_load_gating_prod(g,
184 g->slcg_enabled);
178 if (g->ops.clock_gating.slcg_ltc_load_gating_prod) 185 if (g->ops.clock_gating.slcg_ltc_load_gating_prod)
179 g->ops.clock_gating.slcg_ltc_load_gating_prod(g, g->slcg_enabled); 186 g->ops.clock_gating.slcg_ltc_load_gating_prod(g,
187 g->slcg_enabled);
180 if (g->ops.clock_gating.slcg_perf_load_gating_prod) 188 if (g->ops.clock_gating.slcg_perf_load_gating_prod)
181 g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled); 189 g->ops.clock_gating.slcg_perf_load_gating_prod(g,
190 g->slcg_enabled);
182 if (g->ops.clock_gating.slcg_priring_load_gating_prod) 191 if (g->ops.clock_gating.slcg_priring_load_gating_prod)
183 g->ops.clock_gating.slcg_priring_load_gating_prod(g, g->slcg_enabled); 192 g->ops.clock_gating.slcg_priring_load_gating_prod(g,
193 g->slcg_enabled);
184 if (g->ops.clock_gating.slcg_pmu_load_gating_prod) 194 if (g->ops.clock_gating.slcg_pmu_load_gating_prod)
185 g->ops.clock_gating.slcg_pmu_load_gating_prod(g, g->slcg_enabled); 195 g->ops.clock_gating.slcg_pmu_load_gating_prod(g,
196 g->slcg_enabled);
186 if (g->ops.clock_gating.slcg_xbar_load_gating_prod) 197 if (g->ops.clock_gating.slcg_xbar_load_gating_prod)
187 g->ops.clock_gating.slcg_xbar_load_gating_prod(g, g->slcg_enabled); 198 g->ops.clock_gating.slcg_xbar_load_gating_prod(g,
199 g->slcg_enabled);
188 gk20a_idle(g); 200 gk20a_idle(g);
189 201
190 dev_info(dev, "SLCG is %s.\n", g->slcg_enabled ? "enabled" : 202 nvgpu_info(g, "SLCG is %s.", g->slcg_enabled ? "enabled" :
191 "disabled"); 203 "disabled");
192 204
193 return count; 205 return count;
@@ -207,13 +219,14 @@ static ssize_t ptimer_scale_factor_show(struct device *dev,
207 struct device_attribute *attr, 219 struct device_attribute *attr,
208 char *buf) 220 char *buf)
209{ 221{
222 struct gk20a *g = get_gk20a(dev);
210 struct gk20a_platform *platform = dev_get_drvdata(dev); 223 struct gk20a_platform *platform = dev_get_drvdata(dev);
211 u32 src_freq_hz = platform->ptimer_src_freq; 224 u32 src_freq_hz = platform->ptimer_src_freq;
212 u32 scaling_factor_fp; 225 u32 scaling_factor_fp;
213 ssize_t res; 226 ssize_t res;
214 227
215 if (!src_freq_hz) { 228 if (!src_freq_hz) {
216 dev_err(dev, "reference clk_m rate is not set correctly\n"); 229 nvgpu_err(g, "reference clk_m rate is not set correctly");
217 return -EINVAL; 230 return -EINVAL;
218 } 231 }
219 232
@@ -239,12 +252,13 @@ static ssize_t ptimer_ref_freq_show(struct device *dev,
239 struct device_attribute *attr, 252 struct device_attribute *attr,
240 char *buf) 253 char *buf)
241{ 254{
255 struct gk20a *g = get_gk20a(dev);
242 struct gk20a_platform *platform = dev_get_drvdata(dev); 256 struct gk20a_platform *platform = dev_get_drvdata(dev);
243 u32 src_freq_hz = platform->ptimer_src_freq; 257 u32 src_freq_hz = platform->ptimer_src_freq;
244 ssize_t res; 258 ssize_t res;
245 259
246 if (!src_freq_hz) { 260 if (!src_freq_hz) {
247 dev_err(dev, "reference clk_m rate is not set correctly\n"); 261 nvgpu_err(g, "reference clk_m rate is not set correctly");
248 return -EINVAL; 262 return -EINVAL;
249 } 263 }
250 264
@@ -263,12 +277,13 @@ static ssize_t ptimer_src_freq_show(struct device *dev,
263 struct device_attribute *attr, 277 struct device_attribute *attr,
264 char *buf) 278 char *buf)
265{ 279{
280 struct gk20a *g = get_gk20a(dev);
266 struct gk20a_platform *platform = dev_get_drvdata(dev); 281 struct gk20a_platform *platform = dev_get_drvdata(dev);
267 u32 src_freq_hz = platform->ptimer_src_freq; 282 u32 src_freq_hz = platform->ptimer_src_freq;
268 ssize_t res; 283 ssize_t res;
269 284
270 if (!src_freq_hz) { 285 if (!src_freq_hz) {
271 dev_err(dev, "reference clk_m rate is not set correctly\n"); 286 nvgpu_err(g, "reference clk_m rate is not set correctly");
272 return -EINVAL; 287 return -EINVAL;
273 } 288 }
274 289
@@ -310,7 +325,7 @@ static ssize_t railgate_enable_store(struct device *dev,
310 g->user_railgate_disabled = true; 325 g->user_railgate_disabled = true;
311 } 326 }
312 327
313 dev_info(dev, "railgate is %s.\n", g->can_railgate ? 328 nvgpu_info(g, "railgate is %s.", g->can_railgate ?
314 "enabled" : "disabled"); 329 "enabled" : "disabled");
315 330
316 return count; 331 return count;
@@ -337,7 +352,7 @@ static ssize_t railgate_delay_store(struct device *dev,
337 int err; 352 int err;
338 353
339 if (!g->can_railgate) { 354 if (!g->can_railgate) {
340 dev_info(dev, "does not support power-gating\n"); 355 nvgpu_info(g, "does not support power-gating");
341 return count; 356 return count;
342 } 357 }
343 358
@@ -346,7 +361,7 @@ static ssize_t railgate_delay_store(struct device *dev,
346 g->railgate_delay = railgate_delay; 361 g->railgate_delay = railgate_delay;
347 pm_runtime_set_autosuspend_delay(dev, g->railgate_delay); 362 pm_runtime_set_autosuspend_delay(dev, g->railgate_delay);
348 } else 363 } else
349 dev_err(dev, "Invalid powergate delay\n"); 364 nvgpu_err(g, "Invalid powergate delay");
350 365
351 /* wake-up system to make rail-gating delay effective immediately */ 366 /* wake-up system to make rail-gating delay effective immediately */
352 err = gk20a_busy(g); 367 err = gk20a_busy(g);
@@ -471,7 +486,7 @@ static ssize_t elpg_enable_store(struct device *dev,
471 } 486 }
472 gk20a_idle(g); 487 gk20a_idle(g);
473 } 488 }
474 dev_info(dev, "ELPG is %s.\n", g->elpg_enabled ? "enabled" : 489 nvgpu_info(g, "ELPG is %s.", g->elpg_enabled ? "enabled" :
475 "disabled"); 490 "disabled");
476 491
477 return count; 492 return count;
@@ -535,7 +550,7 @@ static ssize_t mscg_enable_store(struct device *dev,
535 } 550 }
536 gk20a_idle(g); 551 gk20a_idle(g);
537 } 552 }
538 dev_info(dev, "MSCG is %s.\n", g->mscg_enabled ? "enabled" : 553 nvgpu_info(g, "MSCG is %s.", g->mscg_enabled ? "enabled" :
539 "disabled"); 554 "disabled");
540 555
541 return count; 556 return count;
@@ -638,11 +653,11 @@ static ssize_t aelpg_enable_store(struct device *dev,
638 status = nvgpu_pmu_ap_send_command(g, &ap_cmd, false); 653 status = nvgpu_pmu_ap_send_command(g, &ap_cmd, false);
639 } 654 }
640 } else { 655 } else {
641 dev_info(dev, "PMU is not ready, AELPG request failed\n"); 656 nvgpu_info(g, "PMU is not ready, AELPG request failed");
642 } 657 }
643 gk20a_idle(g); 658 gk20a_idle(g);
644 659
645 dev_info(dev, "AELPG is %s.\n", g->aelpg_enabled ? "enabled" : 660 nvgpu_info(g, "AELPG is %s.", g->aelpg_enabled ? "enabled" :
646 "disabled"); 661 "disabled");
647 662
648 return count; 663 return count;
@@ -744,7 +759,7 @@ static ssize_t force_idle_store(struct device *dev,
744 err = __gk20a_do_idle(g, false); 759 err = __gk20a_do_idle(g, false);
745 if (!err) { 760 if (!err) {
746 g->forced_idle = 1; 761 g->forced_idle = 1;
747 dev_info(dev, "gpu is idle : %d\n", 762 nvgpu_info(g, "gpu is idle : %d",
748 g->forced_idle); 763 g->forced_idle);
749 } 764 }
750 } 765 }
@@ -755,7 +770,7 @@ static ssize_t force_idle_store(struct device *dev,
755 err = __gk20a_do_unidle(g); 770 err = __gk20a_do_unidle(g);
756 if (!err) { 771 if (!err) {
757 g->forced_idle = 0; 772 g->forced_idle = 0;
758 dev_info(dev, "gpu is idle : %d\n", 773 nvgpu_info(g, "gpu is idle : %d",
759 g->forced_idle); 774 g->forced_idle);
760 } 775 }
761 } 776 }
@@ -886,8 +901,35 @@ static ssize_t max_timeslice_us_store(struct device *dev,
886static DEVICE_ATTR(max_timeslice_us, ROOTRW, max_timeslice_us_read, 901static DEVICE_ATTR(max_timeslice_us, ROOTRW, max_timeslice_us_read,
887 max_timeslice_us_store); 902 max_timeslice_us_store);
888 903
904static ssize_t czf_bypass_store(struct device *dev,
905 struct device_attribute *attr, const char *buf, size_t count)
906{
907 struct gk20a *g = get_gk20a(dev);
908 unsigned long val;
909
910 if (kstrtoul(buf, 10, &val) < 0)
911 return -EINVAL;
912
913 if (val >= 4)
914 return -EINVAL;
915
916 g->gr.czf_bypass = val;
917
918 return count;
919}
889 920
890void gk20a_remove_sysfs(struct device *dev) 921static ssize_t czf_bypass_read(struct device *dev,
922 struct device_attribute *attr, char *buf)
923{
924 struct gk20a *g = get_gk20a(dev);
925
926 return sprintf(buf, "%d\n", g->gr.czf_bypass);
927}
928
929static DEVICE_ATTR(czf_bypass, ROOTRW, czf_bypass_read, czf_bypass_store);
930
931
932void nvgpu_remove_sysfs(struct device *dev)
891{ 933{
892 device_remove_file(dev, &dev_attr_elcg_enable); 934 device_remove_file(dev, &dev_attr_elcg_enable);
893 device_remove_file(dev, &dev_attr_blcg_enable); 935 device_remove_file(dev, &dev_attr_blcg_enable);
@@ -919,6 +961,8 @@ void gk20a_remove_sysfs(struct device *dev)
919 nvgpu_nvhost_remove_symlink(get_gk20a(dev)); 961 nvgpu_nvhost_remove_symlink(get_gk20a(dev));
920#endif 962#endif
921 963
964 device_remove_file(dev, &dev_attr_czf_bypass);
965
922 if (strcmp(dev_name(dev), "gpu.0")) { 966 if (strcmp(dev_name(dev), "gpu.0")) {
923 struct kobject *kobj = &dev->kobj; 967 struct kobject *kobj = &dev->kobj;
924 struct device *parent = container_of((kobj->parent), 968 struct device *parent = container_of((kobj->parent),
@@ -927,8 +971,9 @@ void gk20a_remove_sysfs(struct device *dev)
927 } 971 }
928} 972}
929 973
930void gk20a_create_sysfs(struct device *dev) 974int nvgpu_create_sysfs(struct device *dev)
931{ 975{
976 struct gk20a *g = get_gk20a(dev);
932 int error = 0; 977 int error = 0;
933 978
934 error |= device_create_file(dev, &dev_attr_elcg_enable); 979 error |= device_create_file(dev, &dev_attr_elcg_enable);
@@ -958,9 +1003,11 @@ void gk20a_create_sysfs(struct device *dev)
958 error |= device_create_file(dev, &dev_attr_max_timeslice_us); 1003 error |= device_create_file(dev, &dev_attr_max_timeslice_us);
959 1004
960#ifdef CONFIG_TEGRA_GK20A_NVHOST 1005#ifdef CONFIG_TEGRA_GK20A_NVHOST
961 error |= nvgpu_nvhost_create_symlink(get_gk20a(dev)); 1006 error |= nvgpu_nvhost_create_symlink(g);
962#endif 1007#endif
963 1008
1009 error |= device_create_file(dev, &dev_attr_czf_bypass);
1010
964 if (strcmp(dev_name(dev), "gpu.0")) { 1011 if (strcmp(dev_name(dev), "gpu.0")) {
965 struct kobject *kobj = &dev->kobj; 1012 struct kobject *kobj = &dev->kobj;
966 struct device *parent = container_of((kobj->parent), 1013 struct device *parent = container_of((kobj->parent),
@@ -970,6 +1017,7 @@ void gk20a_create_sysfs(struct device *dev)
970 } 1017 }
971 1018
972 if (error) 1019 if (error)
973 dev_err(dev, "Failed to create sysfs attributes!\n"); 1020 nvgpu_err(g, "Failed to create sysfs attributes!\n");
974 1021
1022 return error;
975} 1023}
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h b/drivers/gpu/nvgpu/common/linux/sysfs.h
index f56ccfc7..80925844 100644
--- a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h
+++ b/drivers/gpu/nvgpu/common/linux/sysfs.h
@@ -1,7 +1,5 @@
1/* 1/*
2 * GP10B specific sysfs files 2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 * 3 *
6 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -11,12 +9,16 @@
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details. 11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
14 */ 15 */
16#ifndef NVGPU_SYSFS_H
17#define NVGPU_SYSFS_H
15 18
16#ifndef _GP10B_SYSFS_H_ 19struct device;
17#define _GP10B_SYSFS_H_
18 20
19void gp10b_create_sysfs(struct device *dev); 21int nvgpu_create_sysfs(struct device *dev);
20void gp10b_remove_sysfs(struct device *dev); 22void nvgpu_remove_sysfs(struct device *dev);
21 23
22#endif /*_GP10B_SYSFS_H_*/ 24#endif
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 7dc72f7b..acfb6144 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1419,9 +1419,6 @@ enum {
1419 KEPLER_CHANNEL_GPFIFO_C = 0xA26F, 1419 KEPLER_CHANNEL_GPFIFO_C = 0xA26F,
1420}; 1420};
1421 1421
1422void gk20a_create_sysfs(struct device *dev);
1423void gk20a_remove_sysfs(struct device *dev);
1424
1425#define GK20A_BAR0_IORESOURCE_MEM 0 1422#define GK20A_BAR0_IORESOURCE_MEM 0
1426#define GK20A_BAR1_IORESOURCE_MEM 1 1423#define GK20A_BAR1_IORESOURCE_MEM 1
1427#define GK20A_SIM_IORESOURCE_MEM 2 1424#define GK20A_SIM_IORESOURCE_MEM 2
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c
deleted file mode 100644
index 1c90d2f9..00000000
--- a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * GP10B specific sysfs files
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/platform_device.h>
17
18#include "gk20a/gk20a.h"
19#include "gk20a/platform_gk20a.h"
20#include "gp10b_sysfs.h"
21
22#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
23
24#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH)
25
26static ssize_t czf_bypass_store(struct device *dev,
27 struct device_attribute *attr, const char *buf, size_t count)
28{
29 struct gk20a *g = get_gk20a(dev);
30 unsigned long val;
31
32 if (kstrtoul(buf, 10, &val) < 0)
33 return -EINVAL;
34
35 if (val >= 4)
36 return -EINVAL;
37
38 g->gr.czf_bypass = val;
39
40 return count;
41}
42
43static ssize_t czf_bypass_read(struct device *dev,
44 struct device_attribute *attr, char *buf)
45{
46 struct gk20a *g = get_gk20a(dev);
47
48 return sprintf(buf, "%d\n", g->gr.czf_bypass);
49}
50
51static DEVICE_ATTR(czf_bypass, ROOTRW, czf_bypass_read, czf_bypass_store);
52
53void gp10b_create_sysfs(struct device *dev)
54{
55 struct gk20a *g = get_gk20a(dev);
56 int error = 0;
57
58 g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v();
59
60 error |= device_create_file(dev, &dev_attr_czf_bypass);
61 if (error)
62 nvgpu_err(g, "Failed to create sysfs attributes!");
63}
64
65void gp10b_remove_sysfs(struct device *dev)
66{
67 device_remove_file(dev, &dev_attr_czf_bypass);
68}
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 3bddef4c..f27e2605 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -31,7 +31,6 @@
31 31
32#include "gm20b/gr_gm20b.h" 32#include "gm20b/gr_gm20b.h"
33#include "gp10b/gr_gp10b.h" 33#include "gp10b/gr_gp10b.h"
34#include "gp10b_sysfs.h"
35 34
36#include <nvgpu/hw/gp10b/hw_gr_gp10b.h> 35#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
37#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> 36#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
@@ -2292,6 +2291,8 @@ static int gr_gp10b_init_preemption_state(struct gk20a *g)
2292 gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f()); 2291 gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f());
2293 gk20a_writel(g, gr_debug_2_r(), debug_2); 2292 gk20a_writel(g, gr_debug_2_r(), debug_2);
2294 2293
2294 g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v();
2295
2295 return 0; 2296 return 0;
2296} 2297}
2297 2298
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index 58844e8f..a113d22e 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -23,7 +23,6 @@
23#include "gm20b/pmu_gm20b.h" 23#include "gm20b/pmu_gm20b.h"
24 24
25#include "pmu_gp10b.h" 25#include "pmu_gp10b.h"
26#include "gp10b_sysfs.h"
27 26
28#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> 27#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
29#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> 28#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>