diff options
author | Seema Khowala <seemaj@nvidia.com> | 2016-10-14 16:44:29 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-10-17 17:46:44 -0400 |
commit | 8b051f34fc10caa7309c0ae964fbc708d6a679a2 (patch) | |
tree | 8c0ae62d0c41ca22efca462adb6630517da53b1c /drivers/gpu/nvgpu | |
parent | 70e04628617840f65768a6ec681fa42b042e99e1 (diff) |
gpu: nvgpu: add func ptr for gpc exceptions
Add function ptr for enabling gpc exceptions
JIRA GV11B-28
JIRA GV11B-27
Change-Id: I4c7e4300825bf096c22f229ae7196f324ce40037
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1236902
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 1 |
4 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 933ab4a9..8e0072de 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -275,6 +275,7 @@ struct gpu_ops { | |||
275 | u32 *hww_global_esr); | 275 | u32 *hww_global_esr); |
276 | int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, | 276 | int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, |
277 | bool *post_event); | 277 | bool *post_event); |
278 | void (*enable_gpc_exceptions)(struct gk20a *g); | ||
278 | void (*create_gr_sysfs)(struct device *dev); | 279 | void (*create_gr_sysfs)(struct device *dev); |
279 | u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); | 280 | u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); |
280 | int (*record_sm_error_state)(struct gk20a *g, | 281 | int (*record_sm_error_state)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 7f24747c..1a93d546 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4502,7 +4502,7 @@ static int gr_gk20a_zcull_init_hw(struct gk20a *g, struct gr_gk20a *gr) | |||
4502 | return 0; | 4502 | return 0; |
4503 | } | 4503 | } |
4504 | 4504 | ||
4505 | static void gk20a_gr_enable_gpc_exceptions(struct gk20a *g) | 4505 | void gk20a_gr_enable_gpc_exceptions(struct gk20a *g) |
4506 | { | 4506 | { |
4507 | struct gr_gk20a *gr = &g->gr; | 4507 | struct gr_gk20a *gr = &g->gr; |
4508 | u32 tpc_mask; | 4508 | u32 tpc_mask; |
@@ -4641,7 +4641,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4641 | g->ops.gr.set_hww_esr_report_mask(g); | 4641 | g->ops.gr.set_hww_esr_report_mask(g); |
4642 | 4642 | ||
4643 | /* enable TPC exceptions per GPC */ | 4643 | /* enable TPC exceptions per GPC */ |
4644 | gk20a_gr_enable_gpc_exceptions(g); | 4644 | if (g->ops.gr.enable_gpc_exceptions) |
4645 | g->ops.gr.enable_gpc_exceptions(g); | ||
4645 | 4646 | ||
4646 | /* TBD: ECC for L1/SM */ | 4647 | /* TBD: ECC for L1/SM */ |
4647 | /* TBD: enable per BE exceptions */ | 4648 | /* TBD: enable per BE exceptions */ |
@@ -9113,6 +9114,7 @@ void gk20a_init_gr_ops(struct gpu_ops *gops) | |||
9113 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; | 9114 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; |
9114 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; | 9115 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; |
9115 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; | 9116 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; |
9117 | gops->gr.enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions; | ||
9116 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; | 9118 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; |
9117 | gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; | 9119 | gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; |
9118 | gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; | 9120 | gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 8c08459e..a0179b0d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -657,6 +657,7 @@ int gr_gk20a_suspend_contexts(struct gk20a *g, | |||
657 | int gr_gk20a_resume_contexts(struct gk20a *g, | 657 | int gr_gk20a_resume_contexts(struct gk20a *g, |
658 | struct dbg_session_gk20a *dbg_s, | 658 | struct dbg_session_gk20a *dbg_s, |
659 | int *ctx_resident_ch_fd); | 659 | int *ctx_resident_ch_fd); |
660 | void gk20a_gr_enable_gpc_exceptions(struct gk20a *g); | ||
660 | 661 | ||
661 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) | 662 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) |
662 | { | 663 | { |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 275224e7..a1d032e4 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1551,6 +1551,7 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1551 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; | 1551 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; |
1552 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; | 1552 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; |
1553 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; | 1553 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; |
1554 | gops->gr.enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions; | ||
1554 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; | 1555 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; |
1555 | gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; | 1556 | gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; |
1556 | gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; | 1557 | gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; |