diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-02-19 01:40:37 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-15 02:47:02 -0400 |
commit | 8a1d51fe49da0d2351ee5ece472c8cdf399f0f6a (patch) | |
tree | 1c028329993ce384accef50f10dd4054fdb85fee /drivers/gpu/nvgpu | |
parent | d3f96dfa96a8aafe6f5035e2ed24425141e4202e (diff) |
gpu: nvgpu: gv10x volt policy boardobj changes
- Added support for single rail multi step volt policy & below
are the list of define & struct added/updated to support same.
CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04,
NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04,
Updated struct vbios_voltage_policy_table_1x_entry,
struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set, this holds
members which help to config single rail multi step like delay
between switch step, ramp up & ramp down step size in uv.
- Added case to support SINGLE_RAIL_MULTI_STEP in
volt_volt_policy_construct() based on boardobj type.
- Added case to support SINGLE_RAIL_MULTI_STEP in
volt_get_volt_policy_table() to read data from VBIOS
table vbios_voltage_policy_table_1x_entry & extract to
voltage_policy_single_rail_multi_step.
- Added methods to forward single rail multi step data to
PMU using below methods by assigning data read from
VBIOS voltage_policy_single_rail_multi_step to
nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set
interface.
volt_construct_volt_policy_single_rail_multi_step()
volt_policy_pmu_data_init_sr_multi_step()
volt_policy_pmu_data_init_single_rail()
construct_volt_policy_single_rail()
Change-Id: I17bc8c320777191611365ee63274c38ffe5ecbf7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1660687
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlvolt.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_policy.c | 154 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_policy.h | 9 |
5 files changed, 181 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h index 1a82fbed..dcb8c8ea 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h | |||
@@ -107,6 +107,7 @@ enum nv_pmu_pmgr_pwm_source { | |||
107 | #define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01 | 107 | #define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01 |
108 | #define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02 | 108 | #define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02 |
109 | #define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03 | 109 | #define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03 |
110 | #define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04 | ||
110 | #define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFE | 111 | #define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFE |
111 | #define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFF | 112 | #define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFF |
112 | 113 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 75f8da35..86e009a3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -813,12 +813,15 @@ struct vbios_voltage_policy_table_1x_entry { | |||
813 | u8 type; | 813 | u8 type; |
814 | u32 param0; | 814 | u32 param0; |
815 | u32 param1; | 815 | u32 param1; |
816 | u32 param2; | ||
817 | u32 param3; | ||
816 | } __packed; | 818 | } __packed; |
817 | 819 | ||
818 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 | 820 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 |
819 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 | 821 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 |
820 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 | 822 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 |
821 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 | 823 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 |
824 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04 | ||
822 | 825 | ||
823 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ | 826 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ |
824 | GENMASK(7, 0) | 827 | GENMASK(7, 0) |
@@ -839,6 +842,16 @@ struct vbios_voltage_policy_table_1x_entry { | |||
839 | GENMASK(31, 24) | 842 | GENMASK(31, 24) |
840 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 | 843 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 |
841 | 844 | ||
845 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ | ||
846 | GENMASK(15, 0) | ||
847 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT 0 | ||
848 | #define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_MASK \ | ||
849 | GENMASK(31, 0) | ||
850 | #define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_SHIFT 0 | ||
851 | #define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_MASK \ | ||
852 | GENMASK(31, 0) | ||
853 | #define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_SHIFT 0 | ||
854 | |||
842 | /* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ | 855 | /* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ |
843 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ | 856 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ |
844 | GENMASK(15, 0) | 857 | GENMASK(15, 0) |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h index 3b286139..313a3b2a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | |||
@@ -104,6 +104,7 @@ NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); | |||
104 | /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ | 104 | /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ |
105 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { | 105 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { |
106 | struct nv_pmu_boardobjgrp_e32 super; | 106 | struct nv_pmu_boardobjgrp_e32 super; |
107 | u8 perf_core_vf_seq_policy_idx; | ||
107 | }; | 108 | }; |
108 | 109 | ||
109 | struct nv_pmu_volt_volt_policy_boardobj_set { | 110 | struct nv_pmu_volt_volt_policy_boardobj_set { |
@@ -114,6 +115,13 @@ struct nv_pmu_volt_volt_policy_sr_boardobj_set { | |||
114 | u8 rail_idx; | 115 | u8 rail_idx; |
115 | }; | 116 | }; |
116 | 117 | ||
118 | struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set { | ||
119 | struct nv_pmu_volt_volt_policy_sr_boardobj_set super; | ||
120 | u16 inter_switch_delay_us; | ||
121 | u32 ramp_up_step_size_uv; | ||
122 | u32 ramp_down_step_size_uv; | ||
123 | }; | ||
124 | |||
117 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { | 125 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { |
118 | struct nv_pmu_volt_volt_policy_boardobj_set super; | 126 | struct nv_pmu_volt_volt_policy_boardobj_set super; |
119 | u8 rail_idx_master; | 127 | u8 rail_idx_master; |
@@ -138,6 +146,8 @@ union nv_pmu_volt_volt_policy_boardobj_set_union { | |||
138 | struct nv_pmu_boardobj board_obj; | 146 | struct nv_pmu_boardobj board_obj; |
139 | struct nv_pmu_volt_volt_policy_boardobj_set super; | 147 | struct nv_pmu_volt_volt_policy_boardobj_set super; |
140 | struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; | 148 | struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; |
149 | struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set | ||
150 | single_rail_ms; | ||
141 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; | 151 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; |
142 | struct nv_pmu_volt_volt_policy_srms_boardobj_set | 152 | struct nv_pmu_volt_volt_policy_srms_boardobj_set |
143 | split_rail_m_s; | 153 | split_rail_m_s; |
diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c index 1e34b54f..6f53c721 100644 --- a/drivers/gpu/nvgpu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/volt/volt_policy.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -77,6 +77,97 @@ static u32 construct_volt_policy_split_rail(struct gk20a *g, | |||
77 | return status; | 77 | return status; |
78 | } | 78 | } |
79 | 79 | ||
80 | static u32 construct_volt_policy_single_rail(struct gk20a *g, | ||
81 | struct boardobj **ppboardobj, u16 size, void *pArgs) | ||
82 | { | ||
83 | struct voltage_policy_single_rail *ptmp_policy = | ||
84 | (struct voltage_policy_single_rail *)pArgs; | ||
85 | struct voltage_policy_single_rail *pvolt_policy = NULL; | ||
86 | u32 status = 0; | ||
87 | |||
88 | status = construct_volt_policy(g, ppboardobj, size, pArgs); | ||
89 | if (status) | ||
90 | return status; | ||
91 | |||
92 | pvolt_policy = (struct voltage_policy_single_rail *)*ppboardobj; | ||
93 | |||
94 | pvolt_policy->rail_idx = ptmp_policy->rail_idx; | ||
95 | |||
96 | return status; | ||
97 | } | ||
98 | |||
99 | static u32 volt_policy_pmu_data_init_single_rail(struct gk20a *g, | ||
100 | struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata) | ||
101 | { | ||
102 | u32 status = 0; | ||
103 | struct voltage_policy_single_rail *ppolicy; | ||
104 | struct nv_pmu_volt_volt_policy_sr_boardobj_set *pset; | ||
105 | |||
106 | status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata); | ||
107 | if (status) | ||
108 | goto done; | ||
109 | |||
110 | ppolicy = (struct voltage_policy_single_rail *)pboardobj; | ||
111 | pset = (struct nv_pmu_volt_volt_policy_sr_boardobj_set *) | ||
112 | ppmudata; | ||
113 | pset->rail_idx = ppolicy->rail_idx; | ||
114 | |||
115 | done: | ||
116 | return status; | ||
117 | } | ||
118 | |||
119 | static u32 volt_policy_pmu_data_init_sr_multi_step(struct gk20a *g, | ||
120 | struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata) | ||
121 | { | ||
122 | u32 status = 0; | ||
123 | struct voltage_policy_single_rail_multi_step *ppolicy; | ||
124 | struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *pset; | ||
125 | |||
126 | status = volt_policy_pmu_data_init_single_rail(g, pboardobj, ppmudata); | ||
127 | if (status) | ||
128 | goto done; | ||
129 | |||
130 | ppolicy = (struct voltage_policy_single_rail_multi_step *)pboardobj; | ||
131 | pset = (struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *) | ||
132 | ppmudata; | ||
133 | |||
134 | pset->ramp_up_step_size_uv = ppolicy->ramp_up_step_size_uv; | ||
135 | pset->ramp_down_step_size_uv = ppolicy->ramp_down_step_size_uv; | ||
136 | pset->inter_switch_delay_us = ppolicy->inter_switch_delay_us; | ||
137 | |||
138 | done: | ||
139 | return status; | ||
140 | } | ||
141 | |||
142 | static u32 volt_construct_volt_policy_single_rail_multi_step(struct gk20a *g, | ||
143 | struct boardobj **ppboardobj, u16 size, void *pargs) | ||
144 | { | ||
145 | struct boardobj *pboardobj = NULL; | ||
146 | struct voltage_policy_single_rail_multi_step *p_volt_policy = NULL; | ||
147 | struct voltage_policy_single_rail_multi_step *tmp_policy = | ||
148 | (struct voltage_policy_single_rail_multi_step *)pargs; | ||
149 | u32 status = 0; | ||
150 | |||
151 | status = construct_volt_policy_single_rail(g, ppboardobj, size, pargs); | ||
152 | if (status) | ||
153 | return status; | ||
154 | |||
155 | pboardobj = (*ppboardobj); | ||
156 | p_volt_policy = (struct voltage_policy_single_rail_multi_step *) | ||
157 | *ppboardobj; | ||
158 | |||
159 | pboardobj->pmudatainit = volt_policy_pmu_data_init_sr_multi_step; | ||
160 | |||
161 | p_volt_policy->ramp_up_step_size_uv = | ||
162 | tmp_policy->ramp_up_step_size_uv; | ||
163 | p_volt_policy->ramp_down_step_size_uv = | ||
164 | tmp_policy->ramp_down_step_size_uv; | ||
165 | p_volt_policy->inter_switch_delay_us = | ||
166 | tmp_policy->inter_switch_delay_us; | ||
167 | |||
168 | return status; | ||
169 | } | ||
170 | |||
80 | static u32 volt_policy_pmu_data_init_split_rail(struct gk20a *g, | 171 | static u32 volt_policy_pmu_data_init_split_rail(struct gk20a *g, |
81 | struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata) | 172 | struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata) |
82 | { | 173 | { |
@@ -128,8 +219,8 @@ static struct voltage_policy *volt_volt_policy_construct(struct gk20a *g, void * | |||
128 | struct boardobj *pboard_obj = NULL; | 219 | struct boardobj *pboard_obj = NULL; |
129 | u32 status = 0; | 220 | u32 status = 0; |
130 | 221 | ||
131 | if (BOARDOBJ_GET_TYPE(pargs) == | 222 | switch (BOARDOBJ_GET_TYPE(pargs)) { |
132 | CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP) { | 223 | case CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP: |
133 | status = volt_construct_volt_policy_split_rail_single_step(g, | 224 | status = volt_construct_volt_policy_split_rail_single_step(g, |
134 | &pboard_obj, | 225 | &pboard_obj, |
135 | sizeof(struct voltage_policy_split_rail_single_step), | 226 | sizeof(struct voltage_policy_split_rail_single_step), |
@@ -137,8 +228,20 @@ static struct voltage_policy *volt_volt_policy_construct(struct gk20a *g, void * | |||
137 | if (status) { | 228 | if (status) { |
138 | nvgpu_err(g, | 229 | nvgpu_err(g, |
139 | "Could not allocate memory for voltage_policy"); | 230 | "Could not allocate memory for voltage_policy"); |
140 | pboard_obj = NULL; | 231 | pboard_obj = NULL; |
141 | } | 232 | } |
233 | break; | ||
234 | case CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP: | ||
235 | status = volt_construct_volt_policy_single_rail_multi_step(g, | ||
236 | &pboard_obj, | ||
237 | sizeof(struct voltage_policy_single_rail_multi_step), | ||
238 | pargs); | ||
239 | if (status) { | ||
240 | nvgpu_err(g, | ||
241 | "Could not allocate memory for voltage_policy"); | ||
242 | pboard_obj = NULL; | ||
243 | } | ||
244 | break; | ||
142 | } | 245 | } |
143 | 246 | ||
144 | return (struct voltage_policy *)pboard_obj; | 247 | return (struct voltage_policy *)pboard_obj; |
@@ -155,6 +258,8 @@ static u8 volt_policy_type_convert(u8 vbios_type) | |||
155 | 258 | ||
156 | case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP: | 259 | case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP: |
157 | return CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP; | 260 | return CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP; |
261 | case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP: | ||
262 | return CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP; | ||
158 | } | 263 | } |
159 | 264 | ||
160 | return CTRL_VOLT_POLICY_TYPE_INVALID; | 265 | return CTRL_VOLT_POLICY_TYPE_INVALID; |
@@ -175,6 +280,7 @@ static u32 volt_get_volt_policy_table(struct gk20a *g, | |||
175 | struct boardobj board_obj; | 280 | struct boardobj board_obj; |
176 | struct voltage_policy volt_policy; | 281 | struct voltage_policy volt_policy; |
177 | struct voltage_policy_split_rail split_rail; | 282 | struct voltage_policy_split_rail split_rail; |
283 | struct voltage_policy_single_rail_multi_step single_rail_ms; | ||
178 | } policy_type_data; | 284 | } policy_type_data; |
179 | 285 | ||
180 | voltage_policy_table_ptr = | 286 | voltage_policy_table_ptr = |
@@ -204,7 +310,8 @@ static u32 volt_get_volt_policy_table(struct gk20a *g, | |||
204 | 310 | ||
205 | policy_type = volt_policy_type_convert((u8)entry.type); | 311 | policy_type = volt_policy_type_convert((u8)entry.type); |
206 | 312 | ||
207 | if (policy_type == CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP) { | 313 | switch (policy_type) { |
314 | case CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP: | ||
208 | policy_type_data.split_rail.rail_idx_master = | 315 | policy_type_data.split_rail.rail_idx_master = |
209 | (u8)BIOS_GET_FIELD(entry.param0, | 316 | (u8)BIOS_GET_FIELD(entry.param0, |
210 | NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER); | 317 | NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER); |
@@ -220,6 +327,18 @@ static u32 volt_get_volt_policy_table(struct gk20a *g, | |||
220 | policy_type_data.split_rail.delta_max_vfe_equ_idx = | 327 | policy_type_data.split_rail.delta_max_vfe_equ_idx = |
221 | (u8)BIOS_GET_FIELD(entry.param0, | 328 | (u8)BIOS_GET_FIELD(entry.param0, |
222 | NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX); | 329 | NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX); |
330 | break; | ||
331 | case CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP: | ||
332 | policy_type_data.single_rail_ms.inter_switch_delay_us = | ||
333 | (u16)BIOS_GET_FIELD(entry.param1, | ||
334 | NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE); | ||
335 | policy_type_data.single_rail_ms.ramp_up_step_size_uv = | ||
336 | (u32)BIOS_GET_FIELD(entry.param2, | ||
337 | NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV); | ||
338 | policy_type_data.single_rail_ms.ramp_down_step_size_uv = | ||
339 | (u32)BIOS_GET_FIELD(entry.param3, | ||
340 | NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV); | ||
341 | break; | ||
223 | } | 342 | } |
224 | 343 | ||
225 | policy_type_data.board_obj.type = policy_type; | 344 | policy_type_data.board_obj.type = policy_type; |
@@ -286,6 +405,30 @@ static u32 _volt_policy_devgrp_pmustatus_instget(struct gk20a *g, | |||
286 | return 0; | 405 | return 0; |
287 | } | 406 | } |
288 | 407 | ||
408 | static u32 _volt_policy_grp_pmudatainit_super(struct gk20a *g, | ||
409 | struct boardobjgrp *pboardobjgrp, | ||
410 | struct nv_pmu_boardobjgrp_super *pboardobjgrppmu) | ||
411 | { | ||
412 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header *pset = | ||
413 | (struct nv_pmu_volt_volt_policy_boardobjgrp_set_header *) | ||
414 | pboardobjgrppmu; | ||
415 | struct obj_volt *volt = (struct obj_volt *)pboardobjgrp; | ||
416 | u32 status = 0; | ||
417 | |||
418 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); | ||
419 | if (status) { | ||
420 | nvgpu_err(g, | ||
421 | "error updating pmu boardobjgrp for volt policy 0x%x", | ||
422 | status); | ||
423 | goto done; | ||
424 | } | ||
425 | pset->perf_core_vf_seq_policy_idx = | ||
426 | volt->volt_policy_metadata.perf_core_vf_seq_policy_idx; | ||
427 | |||
428 | done: | ||
429 | return status; | ||
430 | } | ||
431 | |||
289 | u32 volt_policy_pmu_setup(struct gk20a *g) | 432 | u32 volt_policy_pmu_setup(struct gk20a *g) |
290 | { | 433 | { |
291 | u32 status; | 434 | u32 status; |
@@ -326,6 +469,7 @@ u32 volt_policy_sw_setup(struct gk20a *g) | |||
326 | 469 | ||
327 | pboardobjgrp->pmudatainstget = _volt_policy_devgrp_pmudata_instget; | 470 | pboardobjgrp->pmudatainstget = _volt_policy_devgrp_pmudata_instget; |
328 | pboardobjgrp->pmustatusinstget = _volt_policy_devgrp_pmustatus_instget; | 471 | pboardobjgrp->pmustatusinstget = _volt_policy_devgrp_pmustatus_instget; |
472 | pboardobjgrp->pmudatainit = _volt_policy_grp_pmudatainit_super; | ||
329 | 473 | ||
330 | /* Obtain Voltage Rail Table from VBIOS */ | 474 | /* Obtain Voltage Rail Table from VBIOS */ |
331 | status = volt_get_volt_policy_table(g, &g->perf_pmu.volt. | 475 | status = volt_get_volt_policy_table(g, &g->perf_pmu.volt. |
diff --git a/drivers/gpu/nvgpu/volt/volt_policy.h b/drivers/gpu/nvgpu/volt/volt_policy.h index 8db79218..34c8f0f6 100644 --- a/drivers/gpu/nvgpu/volt/volt_policy.h +++ b/drivers/gpu/nvgpu/volt/volt_policy.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -68,6 +68,13 @@ struct voltage_policy_single_rail { | |||
68 | u8 rail_idx; | 68 | u8 rail_idx; |
69 | }; | 69 | }; |
70 | 70 | ||
71 | struct voltage_policy_single_rail_multi_step { | ||
72 | struct voltage_policy_single_rail super; | ||
73 | u16 inter_switch_delay_us; | ||
74 | u32 ramp_up_step_size_uv; | ||
75 | u32 ramp_down_step_size_uv; | ||
76 | }; | ||
77 | |||
71 | u32 volt_policy_sw_setup(struct gk20a *g); | 78 | u32 volt_policy_sw_setup(struct gk20a *g); |
72 | u32 volt_policy_pmu_setup(struct gk20a *g); | 79 | u32 volt_policy_pmu_setup(struct gk20a *g); |
73 | #endif | 80 | #endif |