gpu: nvgpu: PMU init sequence change

-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c
 method nvgpu_init_pmu_support()
-Modified nvgpu_init_pmu_support() to init required interface
 for PMU RTOS & does start PMU RTOS in secure & non-secure
 based on NVGPU_SEC_PRIVSECURITY flag.
-Created secured_pmu_start ops under PMU ops to start PMU
 falcon in low secure mode.
-Updated PMU ops update_lspmu_cmdline_args, setup_apertures &
 secured_pmu_start assignment for gp106 & gv100 to support
 modified PMU init sequence.
-Removed duplicate PMU non-secure bootstrap code from multiple
 files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method
 to handle non secure PMU bootstrap, reused this method
 for need chips.

JIRA NVGPU-1146

Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818099
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

18 files changed, 204 insertions, 163 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index 6d1d5f00..ffc9ec39 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -290,7 +290,7 @@ skip_init:
 int nvgpu_init_pmu_support(struct gk20a *g)
 {
         struct nvgpu_pmu *pmu = &g->pmu;
-        u32 err;
+        int err = 0;
 
         nvgpu_log_fn(g, " ");
 
@@ -298,24 +298,54 @@ int nvgpu_init_pmu_support(struct gk20a *g)
                 return 0;
         }
 
-        err = pmu_enable_hw(pmu, true);
-        if (err) {
-                return err;
-        }
-
         if (g->support_pmu) {
                 err = nvgpu_init_pmu_setup_sw(g);
-                if (err) {
-                        return err;
+                if (err != 0) {
+                        goto exit;
                 }
-                err = g->ops.pmu.pmu_setup_hw_and_bootstrap(g);
-                if (err) {
-                        return err;
+
+                if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
+                        /*
+                         * clear halt interrupt to avoid PMU-RTOS ucode
+                         * hitting breakpoint due to PMU halt
+                         */
+                        err = nvgpu_flcn_clear_halt_intr_status(&g->pmu_flcn,
+                                gk20a_get_gr_idle_timeout(g));
+                        if (err != 0) {
+                                goto exit;
+                        }
+
+                        if (g->ops.pmu.setup_apertures != NULL) {
+                                g->ops.pmu.setup_apertures(g);
+                        }
+
+                        if (g->ops.pmu.update_lspmu_cmdline_args != NULL) {
+                                g->ops.pmu.update_lspmu_cmdline_args(g);
+                        }
+
+                        if (g->ops.pmu.pmu_enable_irq != NULL) {
+                                nvgpu_mutex_acquire(&g->pmu.isr_mutex);
+                                g->ops.pmu.pmu_enable_irq(&g->pmu, true);
+                                g->pmu.isr_enabled = true;
+                                nvgpu_mutex_release(&g->pmu.isr_mutex);
+                        }
+
+                        /*Once in LS mode, cpuctl_alias is only accessible*/
+                        if (g->ops.pmu.secured_pmu_start != NULL) {
+                                g->ops.pmu.secured_pmu_start(g);
+                        }
+                } else {
+                        /* Do non-secure PMU boot */
+                        err = g->ops.pmu.pmu_setup_hw_and_bootstrap(g);
+                        if (err != 0) {
+                                goto exit;
+                        }
                 }
 
                 nvgpu_pmu_state_change(g, PMU_STATE_STARTING, false);
         }
 
+exit:
         return err;
 }
 
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 86cb04d9..f231e088 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -490,40 +490,6 @@ void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set)
         }
 }
 
-int gk20a_init_pmu_setup_hw1(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        int err = 0;
-
-        nvgpu_log_fn(g, " ");
-
-        nvgpu_mutex_acquire(&pmu->isr_mutex);
-        nvgpu_flcn_reset(pmu->flcn);
-        pmu->isr_enabled = true;
-        nvgpu_mutex_release(&pmu->isr_mutex);
-
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-
-        err = g->ops.pmu.pmu_nsbootstrap(pmu);
-
-        return err;
-
-}
-
 void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr)
 {
         gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 700a3a0e..35b80eaf 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -58,7 +58,6 @@ void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set);
 u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id);
 void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id);
 
-int gk20a_init_pmu_setup_hw1(struct gk20a *g);
 void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr);
 bool gk20a_is_pmu_supported(struct gk20a *g);
 
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index a4657ff3..e38e9a85 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -1045,76 +1045,6 @@ int acr_ucode_patch_sig(struct gk20a *g,
         return 0;
 }
 
-int gm20b_init_nspmu_setup_hw1(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        int err = 0;
-
-        nvgpu_log_fn(g, " ");
-
-        nvgpu_mutex_acquire(&pmu->isr_mutex);
-        nvgpu_flcn_reset(pmu->flcn);
-        pmu->isr_enabled = true;
-        nvgpu_mutex_release(&pmu->isr_mutex);
-
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-
-        err = g->ops.pmu.pmu_nsbootstrap(pmu);
-
-        return err;
-}
-
-void gm20b_setup_apertures(struct gk20a *g)
-{
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                        pwr_fbif_transcfg_mem_type_virtual_f());
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-}
-
-void gm20b_update_lspmu_cmdline_args(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        /*Copying pmu cmdline args*/
-        g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
-                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
-        g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
-                pmu, GK20A_PMU_TRACE_BUFSIZE);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
-                pmu, GK20A_PMU_DMAIDX_VIRT);
-        nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
-                (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
-                g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
-}
-
 static int nvgpu_gm20b_acr_wait_for_completion(struct gk20a *g,
         struct nvgpu_falcon *flcn, unsigned int timeout)
 {
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index cae6ab6a..fad40081 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -41,10 +41,6 @@ int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
         void *lsfm, u32 *p_bl_gen_desc_size);
 int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
         void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
-void gm20b_update_lspmu_cmdline_args(struct gk20a *g);
-void gm20b_setup_apertures(struct gk20a *g);
-int gm20b_pmu_setup_sw(struct gk20a *g);
-int gm20b_init_nspmu_setup_hw1(struct gk20a *g);
 
 int acr_ucode_patch_sig(struct gk20a *g,
                 unsigned int *p_img,
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 52f86dab..133428da 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -735,7 +735,8 @@ int gm20b_init_hal(struct gk20a *g)
                         gm20b_flcn_populate_bl_dmem_desc;
                 gops->pmu.update_lspmu_cmdline_args =
                         gm20b_update_lspmu_cmdline_args;
-                gops->pmu.setup_apertures = gm20b_setup_apertures;
+                gops->pmu.setup_apertures = gm20b_pmu_setup_apertures;
+                gops->pmu.secured_pmu_start = gm20b_secured_pmu_start;
 
                 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
                 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
@@ -745,6 +746,8 @@ int gm20b_init_hal(struct gk20a *g)
                 /* Inherit from gk20a */
                 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
                 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob;
+                gops->pmu.pmu_setup_hw_and_bootstrap =
+                        gm20b_ns_pmu_setup_hw_and_bootstrap;
                 gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
 
                 gops->pmu.load_lsfalcon_ucode = NULL;
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 6e764ac5..df0ae58d 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -278,6 +278,72 @@ bool gm20b_pmu_is_debug_mode_en(struct gk20a *g)
         return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U;
 }
 
+int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g)
+{
+        struct nvgpu_pmu *pmu = &g->pmu;
+
+        nvgpu_log_fn(g, " ");
+
+        nvgpu_mutex_acquire(&pmu->isr_mutex);
+        nvgpu_flcn_reset(pmu->flcn);
+        pmu->isr_enabled = true;
+        nvgpu_mutex_release(&pmu->isr_mutex);
+
+        /* setup apertures - virtual */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+                pwr_fbif_transcfg_mem_type_virtual_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+                pwr_fbif_transcfg_mem_type_virtual_f());
+        /* setup apertures - physical */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+                pwr_fbif_transcfg_mem_type_physical_f() |
+                pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+                pwr_fbif_transcfg_mem_type_physical_f() |
+                pwr_fbif_transcfg_target_coherent_sysmem_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+                pwr_fbif_transcfg_mem_type_physical_f() |
+                pwr_fbif_transcfg_target_noncoherent_sysmem_f());
+
+        return g->ops.pmu.pmu_nsbootstrap(pmu);
+}
+
+void gm20b_pmu_setup_apertures(struct gk20a *g)
+{
+        /* setup apertures - virtual */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+                        pwr_fbif_transcfg_mem_type_virtual_f());
+        /* setup apertures - physical */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_coherent_sysmem_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_noncoherent_sysmem_f());
+}
+
+void gm20b_update_lspmu_cmdline_args(struct gk20a *g)
+{
+        struct nvgpu_pmu *pmu = &g->pmu;
+        /*Copying pmu cmdline args*/
+        g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
+                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
+        g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
+                pmu, GK20A_PMU_TRACE_BUFSIZE);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
+                pmu, GK20A_PMU_DMAIDX_VIRT);
+        nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
+                (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
+                g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
+}
 
 static int gm20b_bl_bootstrap(struct gk20a *g,
         struct nvgpu_falcon_bl_info *bl_info)
@@ -337,3 +403,9 @@ int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g,
 exit:
         return err;
 }
+
+void gm20b_secured_pmu_start(struct gk20a *g)
+{
+        gk20a_writel(g, pwr_falcon_cpuctl_alias_r(),
+                pwr_falcon_cpuctl_startcpu_f(1));
+}
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
index 37634783..0e4968fb 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
@@ -34,7 +34,11 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags);
 int gm20b_pmu_init_acr(struct gk20a *g);
 void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr);
 bool gm20b_pmu_is_debug_mode_en(struct gk20a *g);
+int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g);
+void gm20b_pmu_setup_apertures(struct gk20a *g);
+void gm20b_update_lspmu_cmdline_args(struct gk20a *g);
 int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g,
         struct hs_acr *acr_desc,
         struct nvgpu_falcon_bl_info *bl_info);
+void gm20b_secured_pmu_start(struct gk20a *g);
 #endif /*NVGPU_GM20B_PMU_GM20B_H*/
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 048c0a45..3a2fa71d 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -658,6 +658,10 @@ static const struct gpu_ops gp106_ops = {
                 .get_irqdest = gk20a_pmu_get_irqdest,
                 .alloc_super_surface = NULL,
                 .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
+                .update_lspmu_cmdline_args =
+                        gp106_update_lspmu_cmdline_args,
+                .setup_apertures = gp106_pmu_setup_apertures,
+                .secured_pmu_start = gm20b_secured_pmu_start,
         },
         .clk = {
                 .init_clk_support = gp106_init_clk_support,
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
index 031ac7d8..3e4a7390 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -306,3 +306,61 @@ int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
         }
         return 0;
 }
+
+void gp106_update_lspmu_cmdline_args(struct gk20a *g)
+{
+        struct nvgpu_pmu *pmu = &g->pmu;
+
+        /*Copying pmu cmdline args*/
+        g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, 0);
+        g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
+                pmu, GK20A_PMU_TRACE_BUFSIZE);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
+                pmu, GK20A_PMU_DMAIDX_VIRT);
+        if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) {
+                g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu);
+        }
+
+        nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
+                (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
+                g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
+
+}
+
+void gp106_pmu_setup_apertures(struct gk20a *g)
+{
+        struct mm_gk20a *mm = &g->mm;
+
+        /* PMU TRANSCFG */
+        /* setup apertures - virtual */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+                        pwr_fbif_transcfg_mem_type_virtual_f());
+        /* setup apertures - physical */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_coherent_sysmem_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_noncoherent_sysmem_f());
+
+        /* PMU Config */
+        gk20a_writel(g, pwr_falcon_itfen_r(),
+                                gk20a_readl(g, pwr_falcon_itfen_r()) |
+                                pwr_falcon_itfen_ctxen_enable_f());
+        gk20a_writel(g, pwr_pmu_new_instblk_r(),
+                pwr_pmu_new_instblk_ptr_f(
+                        nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
+                pwr_pmu_new_instblk_valid_f(1) |
+                nvgpu_aperture_mask(g, &mm->pmu.inst_block,
+                        pwr_pmu_new_instblk_target_sys_ncoh_f(),
+                        pwr_pmu_new_instblk_target_sys_coh_f(),
+                        pwr_pmu_new_instblk_target_fb_f()));
+}
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.h b/drivers/gpu/nvgpu/gp106/pmu_gp106.h
index 9cf1202e..c9392d7b 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.h
@@ -41,5 +41,7 @@ void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
                 struct pmu_pg_stats_data *pg_stat_data);
 bool gp106_pmu_is_engine_in_reset(struct gk20a *g);
 int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset);
+void gp106_update_lspmu_cmdline_args(struct gk20a *g);
+void gp106_pmu_setup_apertures(struct gk20a *g);
 
 #endif /* NVGPU_PMU_GP106_H */
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 759d271e..740cb8b7 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -794,7 +794,8 @@ int gp10b_init_hal(struct gk20a *g)
                         gm20b_flcn_populate_bl_dmem_desc,
                 gops->pmu.update_lspmu_cmdline_args =
                         gm20b_update_lspmu_cmdline_args;
-                gops->pmu.setup_apertures = gm20b_setup_apertures;
+                gops->pmu.setup_apertures = gm20b_pmu_setup_apertures;
+                gops->pmu.secured_pmu_start = gm20b_secured_pmu_start;
 
                 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
                 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
@@ -806,6 +807,8 @@ int gp10b_init_hal(struct gk20a *g)
                 /* Inherit from gk20a */
                 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
                 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
+                gops->pmu.pmu_setup_hw_and_bootstrap =
+                        gm20b_ns_pmu_setup_hw_and_bootstrap;
                 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
 
                 gops->pmu.load_lsfalcon_ucode = NULL;
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index 5c7d1523..d268ab88 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -304,45 +304,6 @@ void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
                                 0x0);
 }
 
-int gp10b_init_pmu_setup_hw1(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        int err;
-
-        nvgpu_log_fn(g, " ");
-
-        nvgpu_mutex_acquire(&pmu->isr_mutex);
-        nvgpu_flcn_reset(pmu->flcn);
-        pmu->isr_enabled = true;
-        nvgpu_mutex_release(&pmu->isr_mutex);
-
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-
-        err = g->ops.pmu.pmu_nsbootstrap(pmu);
-        if (err) {
-                return err;
-        }
-
-        nvgpu_log_fn(g, "done");
-        return 0;
-
-}
-
 bool gp10b_is_lazy_bootstrap(u32 falcon_id)
 {
         bool enable_status = false;
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
index 87c3ba79..4fd4c7c4 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * GP10B PMU
  *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -31,7 +31,6 @@ struct gk20a;
 bool gp10b_is_lazy_bootstrap(u32 falcon_id);
 bool gp10b_is_priv_load(u32 falcon_id);
 bool gp10b_is_pmu_supported(struct gk20a *g);
-int gp10b_init_pmu_setup_hw1(struct gk20a *g);
 void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
                 struct pmu_pg_stats_data *pg_stat_data);
 int gp10b_pmu_setup_elpg(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 45c3adb3..99ee2d10 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -757,6 +757,10 @@ static const struct gpu_ops gv100_ops = {
                 .get_irqdest = gk20a_pmu_get_irqdest,
                 .alloc_super_surface = nvgpu_pmu_super_surface_alloc,
                 .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
+                .update_lspmu_cmdline_args =
+                        gp106_update_lspmu_cmdline_args,
+                .setup_apertures = gp106_pmu_setup_apertures,
+                .secured_pmu_start = gm20b_secured_pmu_start,
         },
         .clk = {
                 .init_clk_support = gp106_init_clk_support,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 18b00ea4..665e2ed1 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -888,6 +888,7 @@ int gv11b_init_hal(struct gk20a *g)
                 gops->pmu.update_lspmu_cmdline_args =
                         gm20b_update_lspmu_cmdline_args;
                 gops->pmu.setup_apertures = gv11b_setup_apertures;
+                gops->pmu.secured_pmu_start = gm20b_secured_pmu_start;
 
                 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
                 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
@@ -898,6 +899,8 @@ int gv11b_init_hal(struct gk20a *g)
         } else {
                 /* Inherit from gk20a */
                 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
+                gops->pmu.pmu_setup_hw_and_bootstrap =
+                        gm20b_ns_pmu_setup_hw_and_bootstrap;
 
                 gops->pmu.load_lsfalcon_ucode = NULL;
                 gops->pmu.init_wpr_region = NULL;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 892aa9af..d0f51055 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1066,6 +1066,7 @@ struct gpu_ops {
                 int (*alloc_super_surface)(struct gk20a *g,
                         struct nvgpu_mem *super_surface, u32 size);
                 bool (*is_debug_mode_enabled)(struct gk20a *g);
+                void (*secured_pmu_start)(struct gk20a *g);
         } pmu;
         struct {
                 int (*init_debugfs)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 9b3b4ed5..78aef699 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -614,6 +614,10 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
                         gm20b_pmu_populate_loader_cfg,
                 gops->pmu.flcn_populate_bl_dmem_desc =
                         gm20b_flcn_populate_bl_dmem_desc,
+                gops->pmu.update_lspmu_cmdline_args =
+                        gm20b_update_lspmu_cmdline_args;
+                gops->pmu.setup_apertures = gm20b_pmu_setup_apertures;
+                gops->pmu.secured_pmu_start = gm20b_secured_pmu_start;
 
                 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
                 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
@@ -625,6 +629,8 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
                 /* Inherit from gk20a */
                 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
                 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
+                gops->pmu.pmu_setup_hw_and_bootstrap =
+                        gm20b_ns_pmu_setup_hw_and_bootstrap;
                 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
 
                 gops->pmu.load_lsfalcon_ucode = NULL;