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authorKonsta Holtta <kholtta@nvidia.com>2018-09-11 07:35:19 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2019-08-15 03:58:15 -0400
commit8281262187c50be841a83a5b99e2485836922269 (patch)
tree58885b8d2e7f894ecc964fb21c0643245210d383 /drivers/gpu/nvgpu
parenteca2cf043e3f52734e2fbba68631a2ef70dad76d (diff)
gpu: nvgpu: add usermode_base HAL
Add a HAL function pointer to fifo to for reading the usermode_cfg0 register and implement it for gv11b. Bug 200145225 Bug 200541476 Change-Id: I5f77b15d3b502d9370b1f14129314eaf51a9d7d1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811839 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit fddb2969240652e1a56089b249684b55430d45c5 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170004 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c4
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.h1
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c1
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/gk20a.h1
4 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index 36cb5306..be4d56a8 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -220,6 +220,10 @@ int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
220 return channel_gp10b_commit_userd(c); 220 return channel_gp10b_commit_userd(c);
221} 221}
222 222
223u64 gv11b_fifo_usermode_base(struct gk20a *g)
224{
225 return usermode_cfg0_r();
226}
223 227
224void gv11b_ring_channel_doorbell(struct channel_gk20a *c) 228void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
225{ 229{
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
index bc6b0f1c..abbf77a6 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
@@ -133,4 +133,5 @@ void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g,
133 struct channel_gk20a *ch, struct nvgpu_mem *mem); 133 struct channel_gk20a *ch, struct nvgpu_mem *mem);
134void gv11b_userd_writeback_config(struct gk20a *g); 134void gv11b_userd_writeback_config(struct gk20a *g);
135void gv11b_ring_channel_doorbell(struct channel_gk20a *c); 135void gv11b_ring_channel_doorbell(struct channel_gk20a *c);
136u64 gv11b_fifo_usermode_base(struct gk20a *g);
136#endif 137#endif
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 2225e380..ea9b41d8 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -641,6 +641,7 @@ static const struct gpu_ops gv11b_ops = {
641 .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, 641 .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size,
642 .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, 642 .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size,
643 .add_sema_cmd = gv11b_fifo_add_sema_cmd, 643 .add_sema_cmd = gv11b_fifo_add_sema_cmd,
644 .usermode_base = gv11b_fifo_usermode_base,
644 }, 645 },
645 .gr_ctx = { 646 .gr_ctx = {
646 .get_netlist_name = gr_gv11b_get_netlist_name, 647 .get_netlist_name = gr_gv11b_get_netlist_name,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index d523cf5f..feae7d23 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -763,6 +763,7 @@ struct gpu_ops {
763 u32 count, u32 buffer_index); 763 u32 count, u32 buffer_index);
764 int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id); 764 int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id);
765 void (*ring_channel_doorbell)(struct channel_gk20a *c); 765 void (*ring_channel_doorbell)(struct channel_gk20a *c);
766 u64 (*usermode_base)(struct gk20a *g);
766 u32 (*get_sema_wait_cmd_size)(void); 767 u32 (*get_sema_wait_cmd_size)(void);
767 u32 (*get_sema_incr_cmd_size)(void); 768 u32 (*get_sema_incr_cmd_size)(void);
768 void (*add_sema_cmd)(struct gk20a *g, 769 void (*add_sema_cmd)(struct gk20a *g,