gpu: ngpu: gv11b: support hub interrupt

Hub interrupt handler will be added later

JIRA GPUT19X-7

Change-Id: I892e392c6c1fe7d92795b2cab2301f2e68e787c3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313453
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

2 files changed, 26 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
index 9588287f..61b23711 100644
--- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
@@ -23,6 +23,7 @@
 #include "gv11b/fb_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
 
 static void gv11b_init_uncompressed_kind_map(void)
 {
@@ -73,10 +74,26 @@ static void gv11b_init_kind_attr(void)
         }
 }
 
+static void gv11b_fb_hub_isr(struct gk20a *g)
+{
+        u32 niso_intr = gk20a_readl(g, fb_niso_intr_r());
+
+        gk20a_dbg_info("enter hub isr, niso_intr = 0x%x", niso_intr);
+
+        if (niso_intr &
+                 (fb_niso_intr_hub_access_counter_notify_pending_f() |
+                  fb_niso_intr_hub_access_counter_error_pending_f())) {
+
+                gk20a_dbg_info("hub access counter notify/error");
+        } else {
+                gk20a_dbg_info("mmu fault : TODO");
+        }
+}
+
 void gv11b_init_fb(struct gpu_ops *gops)
 {
         gp10b_init_fb(gops);
-
+        gops->fb.hub_isr = gv11b_fb_hub_isr;
         gv11b_init_uncompressed_kind_map();
         gv11b_init_kind_attr();
 
diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
index 83c03029..c901fd76 100644
--- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
@@ -31,10 +31,12 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
                                 0xffffffff);
         g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
                                 mc_intr_pfifo_pending_f() |
+                                mc_intr_hub_pending_f() |
                                 mc_intr_priv_ring_pending_f() |
                                 mc_intr_pbus_pending_f() |
                                 mc_intr_ltc_pending_f() |
                                 eng_intr_mask;
+
         gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
                         g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
 
@@ -47,8 +49,14 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
                         g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
 }
 
+static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
+{
+        return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false);
+}
+
 void gv11b_init_mc(struct gpu_ops *gops)
 {
         gp10b_init_mc(gops);
         gops->mc.intr_enable = mc_gv11b_intr_enable;
+        gops->mc.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending;
 }