gpu: nvgpu: falcon bootstrap support

- Added falcon interface/HAL to bootstrap
falcon by taking boot vector as parameter
- Replaced falcon bootstrap code in multiple
files with nvgpu_flcn_bootstrap() method

JIRA NVGPU-102

Change-Id: I4324824c50c6196d8b7ecf981f815ec778da2fd9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1513643
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

7 files changed, 44 insertions, 30 deletions

diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c
index 74d78e86..4c879e52 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon.c
@@ -196,6 +196,20 @@ int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn,
         return status;
 }
 
+int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector)
+{
+        struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
+        int status = -EINVAL;
+
+        if (flcn_ops->bootstrap)
+                status = flcn_ops->bootstrap(flcn, boot_vector);
+        else
+                nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
+                        flcn->flcn_id);
+
+        return status;
+}
+
 void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id)
 {
         struct nvgpu_falcon *flcn = NULL;
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
index 158f4d8b..0ef10a56 100644
--- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
@@ -324,6 +324,26 @@ static int gk20a_flcn_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst,
         return 0;
 }
 
+static int gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn,
+        u32 boot_vector)
+{
+        struct gk20a *g = flcn->g;
+        u32 base_addr = flcn->flcn_base;
+
+        nvgpu_log_info(g, "boot vec 0x%x", boot_vector);
+
+        gk20a_writel(g, base_addr + falcon_falcon_dmactl_r(),
+                falcon_falcon_dmactl_require_ctx_f(0));
+
+        gk20a_writel(g, base_addr + falcon_falcon_bootvec_r(),
+                falcon_falcon_bootvec_vec_f(boot_vector));
+
+        gk20a_writel(g, base_addr + falcon_falcon_cpuctl_r(),
+                falcon_falcon_cpuctl_startcpu_f(1));
+
+        return 0;
+}
+
 static void gk20a_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
 {
         struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
@@ -357,6 +377,7 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn)
         flcn_ops->copy_from_dmem = gk20a_flcn_copy_from_dmem;
         flcn_ops->copy_to_dmem = gk20a_flcn_copy_to_dmem;
         flcn_ops->copy_to_imem = gk20a_flcn_copy_to_imem;
+        flcn_ops->bootstrap = gk20a_falcon_bootstrap;
 
         gk20a_falcon_engine_dependency_ops(flcn);
 }
@@ -396,7 +417,7 @@ static void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
                 nvgpu_mutex_init(&flcn->copy_lock);
                 gk20a_falcon_ops(flcn);
         } else
-                nvgpu_info(g, "falcon 0x%x not supported on %s",
+                nvgpu_log_info(g, "falcon 0x%x not supported on %s",
                         flcn->flcn_id, g->name);
 }
 
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index b3cacb86..7cf8c475 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -23,6 +23,7 @@
 #include <nvgpu/log.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/firmware.h>
+#include <nvgpu/falcon.h>
 
 #include "gk20a.h"
 #include "gr_gk20a.h"
@@ -239,11 +240,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu)
                         pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE));
         }
 
-        gk20a_writel(g, pwr_falcon_bootvec_r(),
-                pwr_falcon_bootvec_vec_f(desc->bootloader_entry_point));
-
-        gk20a_writel(g, pwr_falcon_cpuctl_r(),
-                pwr_falcon_cpuctl_startcpu_f(1));
+        nvgpu_flcn_bootstrap(g->pmu.flcn, desc->bootloader_entry_point);
 
         gk20a_writel(g, pwr_falcon_os_r(), desc->app_version);
 
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c
index 14610120..13f5023a 100644
--- a/drivers/gpu/nvgpu/gm206/bios_gm206.c
+++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c
@@ -101,12 +101,7 @@ static int gm206_bios_devinit(struct gk20a *g)
                         g->bios.bootscripts_size,
                         0);
 
-        gk20a_writel(g, pwr_falcon_bootvec_r(),
-                pwr_falcon_bootvec_vec_f(g->bios.devinit.code_entry_point));
-        gk20a_writel(g, pwr_falcon_dmactl_r(),
-                        pwr_falcon_dmactl_require_ctx_f(0));
-        gk20a_writel(g, pwr_falcon_cpuctl_r(),
-                pwr_falcon_cpuctl_startcpu_f(1));
+        nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.devinit.code_entry_point);
 
         nvgpu_timeout_init(g, &timeout,
                            PMU_BOOT_TIMEOUT_MAX /
@@ -155,12 +150,7 @@ static int gm206_bios_preos(struct gk20a *g)
                         g->bios.preos.dmem_size,
                         0);
 
-        gk20a_writel(g, pwr_falcon_bootvec_r(),
-                pwr_falcon_bootvec_vec_f(g->bios.preos.code_entry_point));
-        gk20a_writel(g, pwr_falcon_dmactl_r(),
-                        pwr_falcon_dmactl_require_ctx_f(0));
-        gk20a_writel(g, pwr_falcon_cpuctl_r(),
-                pwr_falcon_cpuctl_startcpu_f(1));
+        nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.preos.code_entry_point);
 
         if (nvgpu_flcn_wait_for_halt(g->pmu.flcn,
                 PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT)) {
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 3a638373..1bc51a7c 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -1251,11 +1251,8 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu,
         gm20b_dbg_pmu("Before starting falcon with BL\n");
 
         virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8;
-        gk20a_writel(g, pwr_falcon_bootvec_r(),
-                        pwr_falcon_bootvec_vec_f(virt_addr));
 
-        gk20a_writel(g, pwr_falcon_cpuctl_r(),
-                        pwr_falcon_cpuctl_startcpu_f(1));
+        nvgpu_flcn_bootstrap(pmu->flcn, virt_addr);
 
         return 0;
 }
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index ccd1b3ad..f5e7f2be 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -110,11 +110,8 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
         gk20a_writel(g, psec_falcon_mailbox0_r(), 0xDEADA5A5);
 
         virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8;
-        gk20a_writel(g, psec_falcon_bootvec_r(),
-                        psec_falcon_bootvec_vec_f(virt_addr));
 
-        gk20a_writel(g, psec_falcon_cpuctl_r(),
-                        psec_falcon_cpuctl_startcpu_f(1));
+        nvgpu_flcn_bootstrap(&g->sec2_flcn, virt_addr);
 
         return 0;
 }
@@ -198,10 +195,6 @@ int init_sec2_setup_hw1(struct gk20a *g,
         data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f();
         gk20a_writel(g, psec_fbif_ctl_r(), data);
 
-        data = gk20a_readl(g, psec_falcon_dmactl_r());
-        data &= ~(psec_falcon_dmactl_require_ctx_f(1));
-        gk20a_writel(g, psec_falcon_dmactl_r(), data);
-
         /* setup apertures - virtual */
         gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
                         psec_fbif_transcfg_mem_type_physical_f() |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
index 36e9ffb1..cbda2ee3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -146,6 +146,7 @@ struct nvgpu_falcon_ops {
         u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index);
         void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index,
                 u32 data);
+        int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector);
         void (*dump_falcon_stats)(struct nvgpu_falcon *flcn);
 };
 
@@ -187,6 +188,7 @@ int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn,
 u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index);
 void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index,
         u32 data);
+int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector);
 void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn);
 
 void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id);