diff options
author | Seema Khowala <seemaj@nvidia.com> | 2018-04-18 19:18:59 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-01 19:33:11 -0400 |
commit | 744f7f049867c83ecb2c76681cb80ec789459491 (patch) | |
tree | 15fb1bef19a32921d7c33fb8668e773a6bf62a0d /drivers/gpu/nvgpu | |
parent | d61d72bfb51e8ac8375b85dd9125e146ba60fe0e (diff) |
gpu: nvgpu: add gr hal for fecs_ctxsw_mailbox size
fecs_ctxsw_mailbox_size varies per chip. Use hal to
get the size. Also dump fecs_ctxsw_status_1 to help
debug
Bug 2093809
Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698026
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 |
7 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 65750a15..e48af08c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -474,6 +474,7 @@ struct gpu_ops { | |||
474 | u32 num_fbpas, | 474 | u32 num_fbpas, |
475 | u32 *priv_addr_table, | 475 | u32 *priv_addr_table, |
476 | u32 *priv_addr_table_index); | 476 | u32 *priv_addr_table_index); |
477 | u32 (*fecs_ctxsw_mailbox_size)(void); | ||
477 | } gr; | 478 | } gr; |
478 | struct { | 479 | struct { |
479 | void (*init_hw)(struct gk20a *g); | 480 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 51bb2551..d26d8a93 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -155,8 +155,10 @@ void gk20a_fecs_dump_falcon_stats(struct gk20a *g) | |||
155 | gk20a_readl(g, gr_fecs_debug1_r())); | 155 | gk20a_readl(g, gr_fecs_debug1_r())); |
156 | nvgpu_err(g, "gr_fecs_debuginfo_r : 0x%x", | 156 | nvgpu_err(g, "gr_fecs_debuginfo_r : 0x%x", |
157 | gk20a_readl(g, gr_fecs_debuginfo_r())); | 157 | gk20a_readl(g, gr_fecs_debuginfo_r())); |
158 | nvgpu_err(g, "gr_fecs_ctxsw_status_1_r : 0x%x", | ||
159 | gk20a_readl(g, gr_fecs_ctxsw_status_1_r())); | ||
158 | 160 | ||
159 | for (i = 0; i < gr_fecs_ctxsw_mailbox__size_1_v(); i++) | 161 | for (i = 0; i < g->ops.gr.fecs_ctxsw_mailbox_size(); i++) |
160 | nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d) : 0x%x", | 162 | nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d) : 0x%x", |
161 | i, gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(i))); | 163 | i, gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(i))); |
162 | 164 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 9fc3a494..76837ab7 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -324,6 +324,7 @@ static const struct gpu_ops gm20b_ops = { | |||
324 | .get_pmm_per_chiplet_offset = | 324 | .get_pmm_per_chiplet_offset = |
325 | gr_gm20b_get_pmm_per_chiplet_offset, | 325 | gr_gm20b_get_pmm_per_chiplet_offset, |
326 | .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr, | 326 | .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr, |
327 | .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v, | ||
327 | }, | 328 | }, |
328 | .fb = { | 329 | .fb = { |
329 | .reset = fb_gk20a_reset, | 330 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index d1b60af5..43b1d2e0 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -97,6 +97,7 @@ | |||
97 | #include <nvgpu/hw/gp106/hw_top_gp106.h> | 97 | #include <nvgpu/hw/gp106/hw_top_gp106.h> |
98 | #include <nvgpu/hw/gp106/hw_pram_gp106.h> | 98 | #include <nvgpu/hw/gp106/hw_pram_gp106.h> |
99 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | 99 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> |
100 | #include <nvgpu/hw/gp106/hw_gr_gp106.h> | ||
100 | 101 | ||
101 | 102 | ||
102 | static int gp106_get_litter_value(struct gk20a *g, int value) | 103 | static int gp106_get_litter_value(struct gk20a *g, int value) |
@@ -387,6 +388,7 @@ static const struct gpu_ops gp106_ops = { | |||
387 | .get_pmm_per_chiplet_offset = | 388 | .get_pmm_per_chiplet_offset = |
388 | gr_gm20b_get_pmm_per_chiplet_offset, | 389 | gr_gm20b_get_pmm_per_chiplet_offset, |
389 | .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr, | 390 | .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr, |
391 | .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v, | ||
390 | }, | 392 | }, |
391 | .fb = { | 393 | .fb = { |
392 | .reset = gp106_fb_reset, | 394 | .reset = gp106_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a8ee7412..42350dbc 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -80,6 +80,7 @@ | |||
80 | #include <nvgpu/hw/gp10b/hw_top_gp10b.h> | 80 | #include <nvgpu/hw/gp10b/hw_top_gp10b.h> |
81 | #include <nvgpu/hw/gp10b/hw_pram_gp10b.h> | 81 | #include <nvgpu/hw/gp10b/hw_pram_gp10b.h> |
82 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> | 82 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> |
83 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | ||
83 | 84 | ||
84 | int gp10b_get_litter_value(struct gk20a *g, int value) | 85 | int gp10b_get_litter_value(struct gk20a *g, int value) |
85 | { | 86 | { |
@@ -355,6 +356,7 @@ static const struct gpu_ops gp10b_ops = { | |||
355 | .get_pmm_per_chiplet_offset = | 356 | .get_pmm_per_chiplet_offset = |
356 | gr_gm20b_get_pmm_per_chiplet_offset, | 357 | gr_gm20b_get_pmm_per_chiplet_offset, |
357 | .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr, | 358 | .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr, |
359 | .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v, | ||
358 | }, | 360 | }, |
359 | .fb = { | 361 | .fb = { |
360 | .reset = fb_gk20a_reset, | 362 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index d972d4a5..fbf6e046 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -111,6 +111,7 @@ | |||
111 | #include <nvgpu/hw/gv100/hw_top_gv100.h> | 111 | #include <nvgpu/hw/gv100/hw_top_gv100.h> |
112 | #include <nvgpu/hw/gv100/hw_pram_gv100.h> | 112 | #include <nvgpu/hw/gv100/hw_pram_gv100.h> |
113 | #include <nvgpu/hw/gv100/hw_pwr_gv100.h> | 113 | #include <nvgpu/hw/gv100/hw_pwr_gv100.h> |
114 | #include <nvgpu/hw/gv100/hw_gr_gv100.h> | ||
114 | 115 | ||
115 | static int gv100_get_litter_value(struct gk20a *g, int value) | 116 | static int gv100_get_litter_value(struct gk20a *g, int value) |
116 | { | 117 | { |
@@ -434,6 +435,7 @@ static const struct gpu_ops gv100_ops = { | |||
434 | .get_pmm_per_chiplet_offset = | 435 | .get_pmm_per_chiplet_offset = |
435 | gr_gv11b_get_pmm_per_chiplet_offset, | 436 | gr_gv11b_get_pmm_per_chiplet_offset, |
436 | .split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr, | 437 | .split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr, |
438 | .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v, | ||
437 | }, | 439 | }, |
438 | .fb = { | 440 | .fb = { |
439 | .reset = gv100_fb_reset, | 441 | .reset = gv100_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 47f832a6..a2ee3206 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -93,6 +93,7 @@ | |||
93 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> | 93 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> |
94 | #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> | 94 | #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> |
95 | #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> | 95 | #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> |
96 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | ||
96 | 97 | ||
97 | int gv11b_get_litter_value(struct gk20a *g, int value) | 98 | int gv11b_get_litter_value(struct gk20a *g, int value) |
98 | { | 99 | { |
@@ -407,6 +408,7 @@ static const struct gpu_ops gv11b_ops = { | |||
407 | .get_pmm_per_chiplet_offset = | 408 | .get_pmm_per_chiplet_offset = |
408 | gr_gv11b_get_pmm_per_chiplet_offset, | 409 | gr_gv11b_get_pmm_per_chiplet_offset, |
409 | .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr, | 410 | .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr, |
411 | .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v, | ||
410 | }, | 412 | }, |
411 | .fb = { | 413 | .fb = { |
412 | .reset = gv11b_fb_reset, | 414 | .reset = gv11b_fb_reset, |