diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-19 12:28:30 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-20 16:58:00 -0400 |
commit | 72ae2dedf56e8d8f252497e7cadc80dd9c90ff81 (patch) | |
tree | 14c73b2c89c74492edb39b0d01dd740c884ec28e /drivers/gpu/nvgpu | |
parent | a21e56d584641202327f64741b06b1cd9633d0f6 (diff) |
gpu: nvgpu: Add HAL op for PMU reset
Sequence to reset PMU is different for iGPU and dGPU. Specialize
and implement iGPU version.
Change-Id: I5b9ff2c018a736bc9e27b90d0942c52706b12a12
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1150540
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 1 |
4 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 275619c9..87cf2459 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -533,6 +533,7 @@ struct gpu_ops { | |||
533 | int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) | 533 | int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) |
534 | (struct gk20a *g, u32 mask); | 534 | (struct gk20a *g, u32 mask); |
535 | void (*dump_secure_fuses)(struct gk20a *g); | 535 | void (*dump_secure_fuses)(struct gk20a *g); |
536 | int (*reset)(struct gk20a *g); | ||
536 | u32 lspmuwprinitdone; | 537 | u32 lspmuwprinitdone; |
537 | u32 lsfloadedfalconid; | 538 | u32 lsfloadedfalconid; |
538 | bool fecsbootstrapdone; | 539 | bool fecsbootstrapdone; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 54b2eef4..8bf382fd 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2757,6 +2757,13 @@ static void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) | |||
2757 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); | 2757 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); |
2758 | } | 2758 | } |
2759 | 2759 | ||
2760 | int gk20a_pmu_reset(struct gk20a *g) | ||
2761 | { | ||
2762 | gk20a_reset(g, mc_enable_pwr_enabled_f()); | ||
2763 | |||
2764 | return 0; | ||
2765 | } | ||
2766 | |||
2760 | void gk20a_init_pmu_ops(struct gpu_ops *gops) | 2767 | void gk20a_init_pmu_ops(struct gpu_ops *gops) |
2761 | { | 2768 | { |
2762 | gops->pmu.prepare_ucode = gk20a_prepare_ucode; | 2769 | gops->pmu.prepare_ucode = gk20a_prepare_ucode; |
@@ -2770,6 +2777,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) | |||
2770 | gops->pmu.pmu_pg_grinit_param = NULL; | 2777 | gops->pmu.pmu_pg_grinit_param = NULL; |
2771 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | 2778 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; |
2772 | gops->pmu.dump_secure_fuses = NULL; | 2779 | gops->pmu.dump_secure_fuses = NULL; |
2780 | gops->pmu.reset = gk20a_pmu_reset; | ||
2773 | } | 2781 | } |
2774 | 2782 | ||
2775 | int gk20a_init_pmu_support(struct gk20a *g) | 2783 | int gk20a_init_pmu_support(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index efe03f13..b8bb18a2 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -1426,5 +1426,6 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | |||
1426 | void *param, u32 handle, u32 status); | 1426 | void *param, u32 handle, u32 status); |
1427 | void gk20a_pmu_elpg_statistics(struct gk20a *g, | 1427 | void gk20a_pmu_elpg_statistics(struct gk20a *g, |
1428 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); | 1428 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); |
1429 | int gk20a_pmu_reset(struct gk20a *g); | ||
1429 | 1430 | ||
1430 | #endif /*__PMU_GK20A_H__*/ | 1431 | #endif /*__PMU_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 34d1c30c..8eb600ef 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -323,4 +323,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops) | |||
323 | gops->pmu.pmu_pg_grinit_param = NULL; | 323 | gops->pmu.pmu_pg_grinit_param = NULL; |
324 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | 324 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; |
325 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b; | 325 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b; |
326 | gops->pmu.reset = gk20a_pmu_reset; | ||
326 | } | 327 | } |