diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-12-07 12:29:40 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-25 17:24:24 -0500 |
commit | 729403f545c5bc26ce208d38db65962596951e0a (patch) | |
tree | f3a503445f6acbfe51b2b3b1b355ed474c77726c /drivers/gpu/nvgpu | |
parent | 758dac5567d3e514ea038d532b7fd86cec83a961 (diff) |
gpu: nvgpu: gv100: INIT WPR region using RPC
- Created nv_pmu_rpc_struct_acr_init_wpr_region struct
- Function gv100_pmu_init_acr() to create & execute
INIT_WPR_REGION using RPC.
- Updated gv100 HAL .init_wpr_region to point
to gv100_pmu_init_acr()
- Added code to handle INIT_WPR_REGION ack in
RPC handler.
Change-Id: I699fa945790689e5f24ad5d3de022efb458662e0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/pmu_gv100.c | 45 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/pmu_gv100.h | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h | 23 |
6 files changed, 112 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 0ad630ff..680a9f4f 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -246,6 +246,7 @@ nvgpu-y += \ | |||
246 | gv100/gr_gv100.o \ | 246 | gv100/gr_gv100.o \ |
247 | gv100/regops_gv100.o \ | 247 | gv100/regops_gv100.o \ |
248 | gv100/hal_gv100.o \ | 248 | gv100/hal_gv100.o \ |
249 | gv100/pmu_gv100.o \ | ||
249 | pstate/pstate.o \ | 250 | pstate/pstate.o \ |
250 | clk/clk_vin.o \ | 251 | clk/clk_vin.o \ |
251 | clk/clk_fll.o \ | 252 | clk/clk_fll.o \ |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index 2811a4b0..77acbafc 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -993,6 +993,15 @@ static void pmu_rpc_handler(struct gk20a *g, struct pmu_msg *msg, | |||
993 | } | 993 | } |
994 | 994 | ||
995 | switch (msg->hdr.unit_id) { | 995 | switch (msg->hdr.unit_id) { |
996 | case PMU_UNIT_ACR: | ||
997 | switch (rpc.function) { | ||
998 | case NV_PMU_RPC_ID_ACR_INIT_WPR_REGION: | ||
999 | nvgpu_pmu_dbg(g, | ||
1000 | "reply NV_PMU_RPC_ID_ACR_INIT_WPR_REGION"); | ||
1001 | g->pmu_lsf_pmu_wpr_init_done = 1; | ||
1002 | break; | ||
1003 | } | ||
1004 | break; | ||
996 | case PMU_UNIT_PERFMON_T18X: | 1005 | case PMU_UNIT_PERFMON_T18X: |
997 | case PMU_UNIT_PERFMON: | 1006 | case PMU_UNIT_PERFMON: |
998 | switch (rpc.function) { | 1007 | switch (rpc.function) { |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f8302621..cf9ca9d8 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -103,6 +103,7 @@ | |||
103 | #include "hal_gv100.h" | 103 | #include "hal_gv100.h" |
104 | #include "gv100/fb_gv100.h" | 104 | #include "gv100/fb_gv100.h" |
105 | #include "gv100/mm_gv100.h" | 105 | #include "gv100/mm_gv100.h" |
106 | #include "gv100/pmu_gv100.h" | ||
106 | 107 | ||
107 | #include <nvgpu/bus.h> | 108 | #include <nvgpu/bus.h> |
108 | #include <nvgpu/debug.h> | 109 | #include <nvgpu/debug.h> |
@@ -572,7 +573,7 @@ static const struct gpu_ops gv100_ops = { | |||
572 | .data032_r = pram_data032_r, | 573 | .data032_r = pram_data032_r, |
573 | }, | 574 | }, |
574 | .pmu = { | 575 | .pmu = { |
575 | .init_wpr_region = gm20b_pmu_init_acr, | 576 | .init_wpr_region = gv100_pmu_init_acr, |
576 | .load_lsfalcon_ucode = gp106_load_falcon_ucode, | 577 | .load_lsfalcon_ucode = gp106_load_falcon_ucode, |
577 | .is_lazy_bootstrap = gp106_is_lazy_bootstrap, | 578 | .is_lazy_bootstrap = gp106_is_lazy_bootstrap, |
578 | .is_priv_load = gp106_is_priv_load, | 579 | .is_priv_load = gp106_is_priv_load, |
diff --git a/drivers/gpu/nvgpu/gv100/pmu_gv100.c b/drivers/gpu/nvgpu/gv100/pmu_gv100.c new file mode 100644 index 00000000..339df6af --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/pmu_gv100.c | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * GV100 PMU | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/pmu.h> | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | |||
29 | int gv100_pmu_init_acr(struct gk20a *g) | ||
30 | { | ||
31 | struct nvgpu_pmu *pmu = &g->pmu; | ||
32 | struct nv_pmu_rpc_struct_acr_init_wpr_region rpc; | ||
33 | int status = 0; | ||
34 | |||
35 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_acr_init_wpr_region)); | ||
36 | rpc.wpr_regionId = 0x1; | ||
37 | rpc.wpr_offset = 0x0; | ||
38 | PMU_RPC_EXECUTE(status, pmu, ACR, INIT_WPR_REGION, &rpc, 0); | ||
39 | if (status) { | ||
40 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
41 | status); | ||
42 | } | ||
43 | |||
44 | return status; | ||
45 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/pmu_gv100.h b/drivers/gpu/nvgpu/gv100/pmu_gv100.h new file mode 100644 index 00000000..5ef34149 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/pmu_gv100.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * GV100 PMU | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef __PMU_GV100_H_ | ||
26 | #define __PMU_GV100_H_ | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | int gv100_pmu_init_acr(struct gk20a *g); | ||
31 | |||
32 | #endif /*__PMU_GV100_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h index 2d31207f..bc3b1056 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -110,4 +110,25 @@ struct pmu_acr_msg { | |||
110 | }; | 110 | }; |
111 | }; | 111 | }; |
112 | 112 | ||
113 | /* ACR RPC */ | ||
114 | #define NV_PMU_RPC_ID_ACR_INIT_WPR_REGION 0x00 | ||
115 | #define NV_PMU_RPC_ID_ACR_WRITE_CBC_BASE 0x01 | ||
116 | #define NV_PMU_RPC_ID_ACR_BOOTSTRAP_FALCON 0x02 | ||
117 | #define NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS 0x03 | ||
118 | #define NV_PMU_RPC_ID_ACR__COUNT 0x04 | ||
119 | |||
120 | /* | ||
121 | * structure that holds data used | ||
122 | * to execute INIT_WPR_REGION RPC. | ||
123 | */ | ||
124 | struct nv_pmu_rpc_struct_acr_init_wpr_region { | ||
125 | /*[IN/OUT] Must be first field in RPC structure */ | ||
126 | struct nv_pmu_rpc_header hdr; | ||
127 | /*[IN] ACR region ID of WPR region */ | ||
128 | u32 wpr_regionId; | ||
129 | /* [IN] WPR offset from startAddress */ | ||
130 | u32 wpr_offset; | ||
131 | u32 scratch[1]; | ||
132 | }; | ||
133 | |||
113 | #endif /* _GPMUIFACR_H_ */ | 134 | #endif /* _GPMUIFACR_H_ */ |