diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-02 19:52:18 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:06:55 -0400 |
commit | 7185dcdbf8292bbdfceae49702107f0661397d21 (patch) | |
tree | b31874659e314c19466b3d2d63b89975cf564932 /drivers/gpu/nvgpu | |
parent | cc698f6b9896342a4ab18a677fa05efd5d677bb6 (diff) |
gpu: nvgpu: gv11b: init resume_single_sm gr ops
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: I0ebbfdad73d6212997a21f9240f5d4bc2f28ab2f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512209
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 71 |
1 files changed, 70 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 84ff1335..f7d5eb62 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1815,7 +1815,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1815 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1815 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1816 | "CILP: resume for gpc %d tpc %d sm %d", | 1816 | "CILP: resume for gpc %d tpc %d sm %d", |
1817 | gpc, tpc, sm); | 1817 | gpc, tpc, sm); |
1818 | gk20a_resume_single_sm(g, gpc, tpc); | 1818 | g->ops.gr.resume_single_sm(g, gpc, tpc, sm); |
1819 | 1819 | ||
1820 | *ignore_debugger = true; | 1820 | *ignore_debugger = true; |
1821 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1821 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
@@ -2844,6 +2844,74 @@ static void gv11b_gr_suspend_all_sms(struct gk20a *g, | |||
2844 | } | 2844 | } |
2845 | } | 2845 | } |
2846 | 2846 | ||
2847 | static void gv11b_gr_resume_single_sm(struct gk20a *g, | ||
2848 | u32 gpc, u32 tpc, u32 sm) | ||
2849 | { | ||
2850 | u32 dbgr_control0, dbgr_status0; | ||
2851 | u32 offset; | ||
2852 | /* | ||
2853 | * The following requires some clarification. Despite the fact that both | ||
2854 | * RUN_TRIGGER and STOP_TRIGGER have the word "TRIGGER" in their | ||
2855 | * names, only one is actually a trigger, and that is the STOP_TRIGGER. | ||
2856 | * Merely writing a 1(_TASK) to the RUN_TRIGGER is not sufficient to | ||
2857 | * resume the gpu - the _STOP_TRIGGER must explicitly be set to 0 | ||
2858 | * (_DISABLE) as well. | ||
2859 | |||
2860 | * Advice from the arch group: Disable the stop trigger first, as a | ||
2861 | * separate operation, in order to ensure that the trigger has taken | ||
2862 | * effect, before enabling the run trigger. | ||
2863 | */ | ||
2864 | |||
2865 | offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) + | ||
2866 | gv11b_gr_sm_offset(g, sm); | ||
2867 | |||
2868 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2869 | "resuming gpc:%d, tpc:%d, sm%d", gpc, tpc, sm); | ||
2870 | dbgr_control0 = gk20a_readl(g, | ||
2871 | gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); | ||
2872 | dbgr_status0 = gk20a_readl(g, | ||
2873 | gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset); | ||
2874 | |||
2875 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2876 | "before stop trigger disable: " | ||
2877 | "dbgr_control0 = 0x%x dbgr_status0: 0x%x", | ||
2878 | dbgr_control0, dbgr_status0); | ||
2879 | |||
2880 | /*De-assert stop trigger */ | ||
2881 | dbgr_control0 = set_field(dbgr_control0, | ||
2882 | gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(), | ||
2883 | gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f()); | ||
2884 | gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + | ||
2885 | offset, dbgr_control0); | ||
2886 | |||
2887 | dbgr_control0 = gk20a_readl(g, | ||
2888 | gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); | ||
2889 | dbgr_status0 = gk20a_readl(g, | ||
2890 | gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset); | ||
2891 | |||
2892 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2893 | "before run trigger: " | ||
2894 | "dbgr_control0 = 0x%x dbgr_status0: 0x%x", | ||
2895 | dbgr_control0, dbgr_status0); | ||
2896 | /* Run trigger */ | ||
2897 | dbgr_control0 |= | ||
2898 | gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(); | ||
2899 | gk20a_writel(g, | ||
2900 | gr_gpc0_tpc0_sm0_dbgr_control0_r() + | ||
2901 | offset, dbgr_control0); | ||
2902 | |||
2903 | dbgr_control0 = gk20a_readl(g, | ||
2904 | gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); | ||
2905 | dbgr_status0 = gk20a_readl(g, | ||
2906 | gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset); | ||
2907 | /* run trigger is not sticky bit. SM clears it immediately */ | ||
2908 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2909 | "after run trigger: " | ||
2910 | "dbgr_control0 = 0x%x dbgr_status0: 0x%x", | ||
2911 | dbgr_control0, dbgr_status0); | ||
2912 | |||
2913 | } | ||
2914 | |||
2847 | void gv11b_init_gr(struct gpu_ops *gops) | 2915 | void gv11b_init_gr(struct gpu_ops *gops) |
2848 | { | 2916 | { |
2849 | gp10b_init_gr(gops); | 2917 | gp10b_init_gr(gops); |
@@ -2915,4 +2983,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2915 | gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; | 2983 | gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; |
2916 | gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; | 2984 | gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; |
2917 | gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; | 2985 | gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; |
2986 | gops->gr.resume_single_sm = gv11b_gr_resume_single_sm; | ||
2918 | } | 2987 | } |