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authorDeepak Nibade <dnibade@nvidia.com>2016-08-17 12:31:43 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-09-08 12:43:51 -0400
commit70cad5fbb593602a49f91e57c04d1da0334b3a49 (patch)
tree12db73aa8275b15b8b9771d6d39590e2228db24f /drivers/gpu/nvgpu
parentf31e575ed6b048f2139eab0433cce7f18e670b28 (diff)
gpu: nvgpu: unify nvgpu and pci probe
We have completely different versions of probe for nvgpu and pci device Extract out common steps into nvgpu_probe() function and separate it out in new file nvgpu_common.c Divide task of nvgpu_probe() into further smaller functions Do platform specific things (like irq handling, memresource management, power management) only in individual probes and then call nvgpu_probe() to complete the common initialization Move all debugfs initialization to common gk20a_debug_init() This also helps to bringup all debug nodes to pci device Pass debugfs_symlink name as a parameter to gk20a_debug_init() This allows us to set separate debugfs symlink for nvgpu and pci device In case of railgating, cde and ce debugfs, check if platform supports them or not Copy vidmem_is_vidmem from platform to mm structure and set it to true for pci device Return from gk20a_scale_init() if we don't have either of governor or qos_notifier Fix gk20a_alloc_debugfs_init() and gk20a_secure_page_alloc() to receive device pointer instead of platform_device Export gk20a_railgating_debugfs_init() so that we can call it from gk20a_debug_init() Jira DNVGPU-56 Jira DNVGPU-58 Change-Id: I3cc048082b0a1e57415a9fb8bfb9eec0f0a280cd Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1204207 (cherry picked from commit add6bb0a3d5bd98131bbe6f62d4358d4d722b0fe) Reviewed-on: http://git-master/r/1204462 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/Makefile.nvgpu1
-rw-r--r--drivers/gpu/nvgpu/gk20a/cde_gk20a.c3
-rw-r--r--drivers/gpu/nvgpu/gk20a/ce2_gk20a.c3
-rw-r--r--drivers/gpu/nvgpu/gk20a/debug_gk20a.c103
-rw-r--r--drivers/gpu/nvgpu/gk20a/debug_gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c177
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h5
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_allocator.c4
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_allocator.h2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_scale.c3
-rw-r--r--drivers/gpu/nvgpu/nvgpu_common.c154
-rw-r--r--drivers/gpu/nvgpu/nvgpu_common.h27
-rw-r--r--drivers/gpu/nvgpu/pci.c74
-rw-r--r--drivers/gpu/nvgpu/vgpu/vgpu.c2
14 files changed, 313 insertions, 247 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu
index 7e703706..5ca2f56f 100644
--- a/drivers/gpu/nvgpu/Makefile.nvgpu
+++ b/drivers/gpu/nvgpu/Makefile.nvgpu
@@ -26,6 +26,7 @@ obj-$(CONFIG_GK20A) := nvgpu.o
26 26
27nvgpu-y := \ 27nvgpu-y := \
28 gk20a/gk20a.o \ 28 gk20a/gk20a.o \
29 nvgpu_common.o \
29 gk20a/sched_gk20a.o \ 30 gk20a/sched_gk20a.o \
30 gk20a/as_gk20a.o \ 31 gk20a/as_gk20a.o \
31 gk20a/ctrl_gk20a.o \ 32 gk20a/ctrl_gk20a.o \
diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
index 6f8c160c..844718a7 100644
--- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
@@ -1653,6 +1653,9 @@ void gk20a_cde_debugfs_init(struct device *dev)
1653 struct gk20a_platform *platform = dev_get_drvdata(dev); 1653 struct gk20a_platform *platform = dev_get_drvdata(dev);
1654 struct gk20a *g = get_gk20a(dev); 1654 struct gk20a *g = get_gk20a(dev);
1655 1655
1656 if (!platform->has_cde)
1657 return;
1658
1656 debugfs_create_u32("cde_parameter", S_IWUSR | S_IRUGO, 1659 debugfs_create_u32("cde_parameter", S_IWUSR | S_IRUGO,
1657 platform->debugfs, &g->cde_app.shader_parameter); 1660 platform->debugfs, &g->cde_app.shader_parameter);
1658 debugfs_create_u32("cde_ctx_count", S_IWUSR | S_IRUGO, 1661 debugfs_create_u32("cde_ctx_count", S_IWUSR | S_IRUGO,
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index 8548ae84..109ec240 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -710,6 +710,9 @@ void gk20a_ce_debugfs_init(struct device *dev)
710 struct gk20a_platform *platform = dev_get_drvdata(dev); 710 struct gk20a_platform *platform = dev_get_drvdata(dev);
711 struct gk20a *g = get_gk20a(dev); 711 struct gk20a *g = get_gk20a(dev);
712 712
713 if (!platform->has_ce)
714 return;
715
713 debugfs_create_u32("ce_app_ctx_count", S_IWUSR | S_IRUGO, 716 debugfs_create_u32("ce_app_ctx_count", S_IWUSR | S_IRUGO,
714 platform->debugfs, &g->ce_app.ctx_count); 717 platform->debugfs, &g->ce_app.ctx_count);
715 debugfs_create_u32("ce_app_state", S_IWUSR | S_IRUGO, 718 debugfs_create_u32("ce_app_state", S_IWUSR | S_IRUGO,
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
index 93580a7f..9a84e2e3 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
@@ -386,30 +386,101 @@ void gk20a_init_debug_ops(struct gpu_ops *gops)
386 gops->debug.show_dump = gk20a_debug_show_dump; 386 gops->debug.show_dump = gk20a_debug_show_dump;
387} 387}
388 388
389void gk20a_debug_init(struct device *dev) 389void gk20a_debug_init(struct device *dev, const char *debugfs_symlink)
390{ 390{
391 struct gk20a_platform *platform = dev_get_drvdata(dev); 391 struct gk20a_platform *platform = dev_get_drvdata(dev);
392#ifdef CONFIG_DEBUG_FS
393 struct gk20a *g = platform->g;
394#endif
392 395
393 platform->debugfs = debugfs_create_dir(dev_name(dev), NULL); 396 platform->debugfs = debugfs_create_dir(dev_name(dev), NULL);
394 if (platform->debugfs) { 397 if (!platform->debugfs)
398 return;
399
400 if (debugfs_symlink)
395 platform->debugfs_alias = 401 platform->debugfs_alias =
396 debugfs_create_symlink("gpu.0", NULL, dev_name(dev)); 402 debugfs_create_symlink(debugfs_symlink,
403 NULL, dev_name(dev));
397 404
398 debugfs_create_file("status", S_IRUGO, platform->debugfs, 405 debugfs_create_file("status", S_IRUGO, platform->debugfs,
399 dev, &gk20a_debug_fops); 406 dev, &gk20a_debug_fops);
400 debugfs_create_file("gr_status", S_IRUGO, platform->debugfs, 407 debugfs_create_file("gr_status", S_IRUGO, platform->debugfs,
401 dev, &gk20a_gr_debug_fops); 408 dev, &gk20a_gr_debug_fops);
402 debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR, 409 debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR,
403 platform->debugfs, &gk20a_debug_trace_cmdbuf); 410 platform->debugfs, &gk20a_debug_trace_cmdbuf);
404 411
405 debugfs_create_u32("ch_wdt_timeout_ms", S_IRUGO|S_IWUSR, 412 debugfs_create_u32("ch_wdt_timeout_ms", S_IRUGO|S_IWUSR,
406 platform->debugfs, &platform->ch_wdt_timeout_ms); 413 platform->debugfs, &platform->ch_wdt_timeout_ms);
407 414
408#if defined(GK20A_DEBUG) 415#if defined(GK20A_DEBUG)
409 debugfs_create_u32("dbg_mask", S_IRUGO|S_IWUSR, 416 debugfs_create_u32("dbg_mask", S_IRUGO|S_IWUSR,
410 platform->debugfs, &gk20a_dbg_mask); 417 platform->debugfs, &gk20a_dbg_mask);
411 debugfs_create_u32("dbg_ftrace", S_IRUGO|S_IWUSR, 418 debugfs_create_u32("dbg_ftrace", S_IRUGO|S_IWUSR,
412 platform->debugfs, &gk20a_dbg_ftrace); 419 platform->debugfs, &gk20a_dbg_ftrace);
413#endif 420#endif
414 } 421
422#ifdef CONFIG_DEBUG_FS
423 spin_lock_init(&g->debugfs_lock);
424
425 g->mm.ltc_enabled = true;
426 g->mm.ltc_enabled_debug = true;
427
428 g->debugfs_ltc_enabled =
429 debugfs_create_bool("ltc_enabled", S_IRUGO|S_IWUSR,
430 platform->debugfs,
431 &g->mm.ltc_enabled_debug);
432
433 g->debugfs_gr_idle_timeout_default =
434 debugfs_create_u32("gr_idle_timeout_default_us",
435 S_IRUGO|S_IWUSR, platform->debugfs,
436 &g->gr_idle_timeout_default);
437 g->debugfs_timeouts_enabled =
438 debugfs_create_bool("timeouts_enabled",
439 S_IRUGO|S_IWUSR,
440 platform->debugfs,
441 &g->timeouts_enabled);
442
443 g->debugfs_bypass_smmu =
444 debugfs_create_bool("bypass_smmu",
445 S_IRUGO|S_IWUSR,
446 platform->debugfs,
447 &g->mm.bypass_smmu);
448 g->debugfs_disable_bigpage =
449 debugfs_create_bool("disable_bigpage",
450 S_IRUGO|S_IWUSR,
451 platform->debugfs,
452 &g->mm.disable_bigpage);
453
454 g->debugfs_timeslice_low_priority_us =
455 debugfs_create_u32("timeslice_low_priority_us",
456 S_IRUGO|S_IWUSR,
457 platform->debugfs,
458 &g->timeslice_low_priority_us);
459 g->debugfs_timeslice_medium_priority_us =
460 debugfs_create_u32("timeslice_medium_priority_us",
461 S_IRUGO|S_IWUSR,
462 platform->debugfs,
463 &g->timeslice_medium_priority_us);
464 g->debugfs_timeslice_high_priority_us =
465 debugfs_create_u32("timeslice_high_priority_us",
466 S_IRUGO|S_IWUSR,
467 platform->debugfs,
468 &g->timeslice_high_priority_us);
469 g->debugfs_runlist_interleave =
470 debugfs_create_bool("runlist_interleave",
471 S_IRUGO|S_IWUSR,
472 platform->debugfs,
473 &g->runlist_interleave);
474
475 gr_gk20a_debugfs_init(g);
476 gk20a_pmu_debugfs_init(g->dev);
477 gk20a_railgating_debugfs_init(g->dev);
478 gk20a_cde_debugfs_init(g->dev);
479 gk20a_ce_debugfs_init(g->dev);
480 gk20a_alloc_debugfs_init(g->dev);
481 gk20a_mm_debugfs_init(g->dev);
482 gk20a_fifo_debugfs_init(g->dev);
483 gk20a_sched_debugfs_init(g->dev);
484#endif
485
415} 486}
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h
index e83076b8..ac8e3236 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h
@@ -35,7 +35,7 @@ void gk20a_debug_output(struct gk20a_debug_output *o,
35void gk20a_debug_dump(struct device *pdev); 35void gk20a_debug_dump(struct device *pdev);
36void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o); 36void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o);
37int gk20a_gr_debug_dump(struct device *pdev); 37int gk20a_gr_debug_dump(struct device *pdev);
38void gk20a_debug_init(struct device *dev); 38void gk20a_debug_init(struct device *dev, const char *debugfs_symlink);
39void gk20a_init_debug_ops(struct gpu_ops *gops); 39void gk20a_init_debug_ops(struct gpu_ops *gops);
40void gk20a_debug_dump_device(void *dev); 40void gk20a_debug_dump_device(void *dev);
41 41
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 1fe1d330..f6bb9445 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -45,6 +45,7 @@
45#include <linux/version.h> 45#include <linux/version.h>
46 46
47#include "gk20a.h" 47#include "gk20a.h"
48#include "nvgpu_common.h"
48#include "debug_gk20a.h" 49#include "debug_gk20a.h"
49#include "ctrl_gk20a.h" 50#include "ctrl_gk20a.h"
50#include "hw_mc_gk20a.h" 51#include "hw_mc_gk20a.h"
@@ -83,8 +84,6 @@
83 84
84#define GK20A_NUM_CDEVS 7 85#define GK20A_NUM_CDEVS 7
85 86
86#define EMC3D_DEFAULT_RATIO 750
87
88#if defined(GK20A_DEBUG) 87#if defined(GK20A_DEBUG)
89u32 gk20a_dbg_mask = GK20A_DEFAULT_DBG_MASK; 88u32 gk20a_dbg_mask = GK20A_DEFAULT_DBG_MASK;
90u32 gk20a_dbg_ftrace; 89u32 gk20a_dbg_ftrace;
@@ -144,11 +143,14 @@ static const struct file_operations railgate_residency_fops = {
144 .release = single_release, 143 .release = single_release,
145}; 144};
146 145
147static int gk20a_railgating_debugfs_init(struct device *dev) 146int gk20a_railgating_debugfs_init(struct device *dev)
148{ 147{
149 struct dentry *d; 148 struct dentry *d;
150 struct gk20a_platform *platform = dev_get_drvdata(dev); 149 struct gk20a_platform *platform = dev_get_drvdata(dev);
151 150
151 if (!platform->can_railgate)
152 return 0;
153
152 d = debugfs_create_file( 154 d = debugfs_create_file(
153 "railgate_residency", S_IRUGO|S_IWUSR, platform->debugfs, dev, 155 "railgate_residency", S_IRUGO|S_IWUSR, platform->debugfs, dev,
154 &railgate_residency_fops); 156 &railgate_residency_fops);
@@ -740,32 +742,15 @@ static int gk20a_init_support(struct platform_device *dev)
740 goto fail; 742 goto fail;
741 } 743 }
742 744
743 g->regs_saved = g->regs;
744 g->bar1_saved = g->bar1;
745
746 /* Get interrupt numbers */
747 g->irq_nonstall = platform_get_irq(dev, 1);
748 if (g->irq_stall < 0 || g->irq_nonstall < 0) {
749 err = -ENXIO;
750 goto fail;
751 }
752
753 if (tegra_cpu_is_asim()) { 745 if (tegra_cpu_is_asim()) {
754 err = gk20a_init_sim_support(dev); 746 err = gk20a_init_sim_support(dev);
755 if (err) 747 if (err)
756 goto fail; 748 goto fail;
757 } 749 }
758 750
759 mutex_init(&g->dbg_sessions_lock);
760 mutex_init(&g->client_lock);
761 mutex_init(&g->ch_wdt_lock);
762 mutex_init(&g->poweroff_lock);
763
764 g->remove_support = gk20a_remove_support;
765 return 0; 751 return 0;
766 752
767 fail: 753 fail:
768 gk20a_remove_support(&dev->dev);
769 return err; 754 return err;
770} 755}
771 756
@@ -1449,13 +1434,13 @@ int gk20a_pm_init(struct device *dev)
1449 return err; 1434 return err;
1450} 1435}
1451 1436
1452static int gk20a_secure_page_alloc(struct platform_device *pdev) 1437int gk20a_secure_page_alloc(struct device *dev)
1453{ 1438{
1454 struct gk20a_platform *platform = platform_get_drvdata(pdev); 1439 struct gk20a_platform *platform = dev_get_drvdata(dev);
1455 int err = 0; 1440 int err = 0;
1456 1441
1457 if (platform->secure_page_alloc) { 1442 if (platform->secure_page_alloc) {
1458 err = platform->secure_page_alloc(&pdev->dev); 1443 err = platform->secure_page_alloc(dev);
1459 if (!err) 1444 if (!err)
1460 platform->secure_alloc_ready = true; 1445 platform->secure_alloc_ready = true;
1461 } 1446 }
@@ -1499,9 +1484,6 @@ static int gk20a_probe(struct platform_device *dev)
1499 return -ENOMEM; 1484 return -ENOMEM;
1500 } 1485 }
1501 1486
1502 init_waitqueue_head(&gk20a->sw_irq_stall_last_handled_wq);
1503 init_waitqueue_head(&gk20a->sw_irq_nonstall_last_handled_wq);
1504
1505 set_gk20a(dev, gk20a); 1487 set_gk20a(dev, gk20a);
1506 gk20a->dev = &dev->dev; 1488 gk20a->dev = &dev->dev;
1507 1489
@@ -1509,6 +1491,7 @@ static int gk20a_probe(struct platform_device *dev)
1509 gk20a->irq_nonstall = platform_get_irq(dev, 1); 1491 gk20a->irq_nonstall = platform_get_irq(dev, 1);
1510 if (gk20a->irq_stall < 0 || gk20a->irq_nonstall < 0) 1492 if (gk20a->irq_stall < 0 || gk20a->irq_nonstall < 0)
1511 return -ENXIO; 1493 return -ENXIO;
1494
1512 err = devm_request_threaded_irq(&dev->dev, 1495 err = devm_request_threaded_irq(&dev->dev,
1513 gk20a->irq_stall, 1496 gk20a->irq_stall,
1514 gk20a_intr_isr_stall, 1497 gk20a_intr_isr_stall,
@@ -1535,36 +1518,19 @@ static int gk20a_probe(struct platform_device *dev)
1535 if (gk20a->irq_stall != gk20a->irq_nonstall) 1518 if (gk20a->irq_stall != gk20a->irq_nonstall)
1536 disable_irq(gk20a->irq_nonstall); 1519 disable_irq(gk20a->irq_nonstall);
1537 1520
1538 err = gk20a_user_init(&dev->dev, INTERFACE_NAME, &nvgpu_class); 1521 err = gk20a_init_support(dev);
1539 if (err) 1522 if (err)
1540 return err; 1523 return err;
1541 1524
1542 gk20a_init_support(dev);
1543
1544 init_rwsem(&gk20a->busy_lock);
1545 mutex_init(&platform->railgate_lock);
1546
1547 spin_lock_init(&gk20a->mc_enable_lock);
1548
1549#ifdef CONFIG_RESET_CONTROLLER 1525#ifdef CONFIG_RESET_CONTROLLER
1550 platform->reset_control = devm_reset_control_get(&dev->dev, NULL); 1526 platform->reset_control = devm_reset_control_get(&dev->dev, NULL);
1551 if (IS_ERR(platform->reset_control)) 1527 if (IS_ERR(platform->reset_control))
1552 platform->reset_control = NULL; 1528 platform->reset_control = NULL;
1553#endif 1529#endif
1554 1530
1555 gk20a_debug_init(&dev->dev); 1531 err = nvgpu_probe(gk20a, "gpu.0", INTERFACE_NAME, &nvgpu_class);
1556
1557 /* Initialize the platform interface. */
1558 err = platform->probe(&dev->dev);
1559 if (err) {
1560 dev_err(&dev->dev, "platform probe failed");
1561 return err;
1562 }
1563
1564 err = gk20a_secure_page_alloc(dev);
1565 if (err) 1532 if (err)
1566 dev_err(&dev->dev, 1533 return err;
1567 "failed to allocate secure buffer %d\n", err);
1568 1534
1569 err = gk20a_pm_init(&dev->dev); 1535 err = gk20a_pm_init(&dev->dev);
1570 if (err) { 1536 if (err) {
@@ -1572,127 +1538,8 @@ static int gk20a_probe(struct platform_device *dev)
1572 return err; 1538 return err;
1573 } 1539 }
1574 1540
1575 gk20a->emc3d_ratio = EMC3D_DEFAULT_RATIO;
1576
1577 /* Initialise scaling */
1578 if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))
1579 gk20a_scale_init(&dev->dev);
1580
1581 /* Set DMA parameters to allow larger sgt lists */
1582 dev->dev.dma_parms = &gk20a->dma_parms;
1583 dma_set_max_seg_size(&dev->dev, UINT_MAX);
1584
1585 gk20a->gr_idle_timeout_default =
1586 CONFIG_GK20A_DEFAULT_TIMEOUT;
1587 if (tegra_platform_is_silicon())
1588 gk20a->timeouts_enabled = true;
1589
1590 gk20a->runlist_interleave = true;
1591
1592 gk20a->timeslice_low_priority_us = 1300;
1593 gk20a->timeslice_medium_priority_us = 2600;
1594 gk20a->timeslice_high_priority_us = 5200;
1595
1596 /* Set up initial power settings. For non-slicon platforms, disable *
1597 * power features and for silicon platforms, read from platform data */
1598 gk20a->slcg_enabled =
1599 tegra_platform_is_silicon() ? platform->enable_slcg : false;
1600 gk20a->blcg_enabled =
1601 tegra_platform_is_silicon() ? platform->enable_blcg : false;
1602 gk20a->elcg_enabled =
1603 tegra_platform_is_silicon() ? platform->enable_elcg : false;
1604 gk20a->elpg_enabled =
1605 tegra_platform_is_silicon() ? platform->enable_elpg : false;
1606 gk20a->aelpg_enabled =
1607 tegra_platform_is_silicon() ? platform->enable_aelpg : false;
1608
1609 /* set default values to aelpg parameters */
1610 gk20a->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US;
1611 gk20a->pmu.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US;
1612 gk20a->pmu.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US;
1613 gk20a->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US;
1614 gk20a->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT;
1615
1616 if (platform->late_probe) {
1617 err = platform->late_probe(&dev->dev);
1618 if (err) {
1619 dev_err(&dev->dev, "late probe failed");
1620 return err;
1621 }
1622 }
1623
1624 gk20a_create_sysfs(&dev->dev);
1625
1626 gk20a->mm.bypass_smmu = platform->bypass_smmu;
1627 gk20a->mm.disable_bigpage = platform->disable_bigpage;
1628 gk20a->mm.has_physical_mode = !is_tegra_hypervisor_mode(); 1541 gk20a->mm.has_physical_mode = !is_tegra_hypervisor_mode();
1629 1542
1630#ifdef CONFIG_DEBUG_FS
1631 spin_lock_init(&gk20a->debugfs_lock);
1632 gk20a->mm.ltc_enabled = true;
1633 gk20a->mm.ltc_enabled_debug = true;
1634 gk20a->debugfs_ltc_enabled =
1635 debugfs_create_bool("ltc_enabled", S_IRUGO|S_IWUSR,
1636 platform->debugfs,
1637 &gk20a->mm.ltc_enabled_debug);
1638 gk20a->mm.ltc_enabled_debug = true;
1639 gk20a->debugfs_gr_idle_timeout_default =
1640 debugfs_create_u32("gr_idle_timeout_default_us",
1641 S_IRUGO|S_IWUSR, platform->debugfs,
1642 &gk20a->gr_idle_timeout_default);
1643 gk20a->debugfs_timeouts_enabled =
1644 debugfs_create_bool("timeouts_enabled",
1645 S_IRUGO|S_IWUSR,
1646 platform->debugfs,
1647 &gk20a->timeouts_enabled);
1648 gk20a->debugfs_bypass_smmu =
1649 debugfs_create_bool("bypass_smmu",
1650 S_IRUGO|S_IWUSR,
1651 platform->debugfs,
1652 &gk20a->mm.bypass_smmu);
1653 gk20a->debugfs_disable_bigpage =
1654 debugfs_create_bool("disable_bigpage",
1655 S_IRUGO|S_IWUSR,
1656 platform->debugfs,
1657 &gk20a->mm.disable_bigpage);
1658
1659 gk20a->debugfs_timeslice_low_priority_us =
1660 debugfs_create_u32("timeslice_low_priority_us",
1661 S_IRUGO|S_IWUSR,
1662 platform->debugfs,
1663 &gk20a->timeslice_low_priority_us);
1664
1665 gk20a->debugfs_timeslice_medium_priority_us =
1666 debugfs_create_u32("timeslice_medium_priority_us",
1667 S_IRUGO|S_IWUSR,
1668 platform->debugfs,
1669 &gk20a->timeslice_medium_priority_us);
1670
1671 gk20a->debugfs_timeslice_high_priority_us =
1672 debugfs_create_u32("timeslice_high_priority_us",
1673 S_IRUGO|S_IWUSR,
1674 platform->debugfs,
1675 &gk20a->timeslice_high_priority_us);
1676
1677 gk20a->debugfs_runlist_interleave =
1678 debugfs_create_bool("runlist_interleave",
1679 S_IRUGO|S_IWUSR,
1680 platform->debugfs,
1681 &gk20a->runlist_interleave);
1682
1683 gr_gk20a_debugfs_init(gk20a);
1684 gk20a_pmu_debugfs_init(&dev->dev);
1685 gk20a_railgating_debugfs_init(&dev->dev);
1686 gk20a_cde_debugfs_init(&dev->dev);
1687 gk20a_ce_debugfs_init(&dev->dev);
1688 gk20a_alloc_debugfs_init(dev);
1689 gk20a_mm_debugfs_init(&dev->dev);
1690 gk20a_fifo_debugfs_init(&dev->dev);
1691 gk20a_sched_debugfs_init(&dev->dev);
1692#endif
1693
1694 gk20a_init_gr(gk20a);
1695
1696 return 0; 1543 return 0;
1697} 1544}
1698 1545
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index c255f8f8..669ef1b9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1205,4 +1205,9 @@ static inline void gk20a_channel_trace_sched_param(
1205 ch->ch_ctx.gr_ctx->compute_preempt_mode : 0)); 1205 ch->ch_ctx.gr_ctx->compute_preempt_mode : 0));
1206} 1206}
1207 1207
1208#ifdef CONFIG_DEBUG_FS
1209int gk20a_railgating_debugfs_init(struct device *dev);
1210#endif
1211
1212int gk20a_secure_page_alloc(struct device *dev);
1208#endif /* GK20A_H */ 1213#endif /* GK20A_H */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.c b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.c
index d9e38200..3b20fa2e 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.c
@@ -168,9 +168,9 @@ void gk20a_fini_alloc_debug(struct gk20a_allocator *a)
168 debugfs_remove(a->debugfs_entry); 168 debugfs_remove(a->debugfs_entry);
169} 169}
170 170
171void gk20a_alloc_debugfs_init(struct platform_device *pdev) 171void gk20a_alloc_debugfs_init(struct device *dev)
172{ 172{
173 struct gk20a_platform *platform = platform_get_drvdata(pdev); 173 struct gk20a_platform *platform = dev_get_drvdata(dev);
174 struct dentry *gpu_root = platform->debugfs; 174 struct dentry *gpu_root = platform->debugfs;
175 175
176 gk20a_alloc_debugfs_root = debugfs_create_dir("allocators", gpu_root); 176 gk20a_alloc_debugfs_root = debugfs_create_dir("allocators", gpu_root);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h
index fbfda881..93865190 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h
@@ -210,7 +210,7 @@ static inline void gk20a_alloc_disable_dbg(struct gk20a_allocator *a)
210 */ 210 */
211extern u32 gk20a_alloc_tracing_on; 211extern u32 gk20a_alloc_tracing_on;
212 212
213void gk20a_alloc_debugfs_init(struct platform_device *pdev); 213void gk20a_alloc_debugfs_init(struct device *dev);
214 214
215#define gk20a_alloc_trace_func() \ 215#define gk20a_alloc_trace_func() \
216 do { \ 216 do { \
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_scale.c b/drivers/gpu/nvgpu/gk20a/gk20a_scale.c
index ec9ca5db..ac28d967 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_scale.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_scale.c
@@ -319,6 +319,9 @@ void gk20a_scale_init(struct device *dev)
319 if (g->scale_profile) 319 if (g->scale_profile)
320 return; 320 return;
321 321
322 if (!platform->devfreq_governor && !platform->qos_notify)
323 return;
324
322 profile = kzalloc(sizeof(*profile), GFP_KERNEL); 325 profile = kzalloc(sizeof(*profile), GFP_KERNEL);
323 326
324 profile->dev = dev; 327 profile->dev = dev;
diff --git a/drivers/gpu/nvgpu/nvgpu_common.c b/drivers/gpu/nvgpu/nvgpu_common.c
new file mode 100644
index 00000000..bdc07e50
--- /dev/null
+++ b/drivers/gpu/nvgpu/nvgpu_common.c
@@ -0,0 +1,154 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/dma-mapping.h>
18
19#include "gk20a/gk20a_scale.h"
20#include "gk20a/gk20a.h"
21
22#define EMC3D_DEFAULT_RATIO 750
23
24static void nvgpu_init_vars(struct gk20a *g)
25{
26 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
27
28 init_waitqueue_head(&g->sw_irq_stall_last_handled_wq);
29 init_waitqueue_head(&g->sw_irq_nonstall_last_handled_wq);
30 gk20a_init_gr(g);
31
32 init_rwsem(&g->busy_lock);
33
34 spin_lock_init(&g->mc_enable_lock);
35
36 mutex_init(&platform->railgate_lock);
37 mutex_init(&g->dbg_sessions_lock);
38 mutex_init(&g->client_lock);
39 mutex_init(&g->ch_wdt_lock);
40 mutex_init(&g->poweroff_lock);
41
42 g->regs_saved = g->regs;
43 g->bar1_saved = g->bar1;
44
45 g->emc3d_ratio = EMC3D_DEFAULT_RATIO;
46
47 /* Set DMA parameters to allow larger sgt lists */
48 g->dev->dma_parms = &g->dma_parms;
49 dma_set_max_seg_size(g->dev, UINT_MAX);
50
51}
52
53static void nvgpu_init_timeout(struct gk20a *g)
54{
55 g->gr_idle_timeout_default = CONFIG_GK20A_DEFAULT_TIMEOUT;
56 if (tegra_platform_is_silicon())
57 g->timeouts_enabled = true;
58}
59
60static void nvgpu_init_timeslice(struct gk20a *g)
61{
62 g->runlist_interleave = true;
63
64 g->timeslice_low_priority_us = 1300;
65 g->timeslice_medium_priority_us = 2600;
66 g->timeslice_high_priority_us = 5200;
67}
68
69static void nvgpu_init_pm_vars(struct gk20a *g)
70{
71 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
72
73 /*
74 * Set up initial power settings. For non-slicon platforms, disable
75 * power features and for silicon platforms, read from platform data
76 */
77 g->slcg_enabled =
78 tegra_platform_is_silicon() ? platform->enable_slcg : false;
79 g->blcg_enabled =
80 tegra_platform_is_silicon() ? platform->enable_blcg : false;
81 g->elcg_enabled =
82 tegra_platform_is_silicon() ? platform->enable_elcg : false;
83 g->elpg_enabled =
84 tegra_platform_is_silicon() ? platform->enable_elpg : false;
85 g->aelpg_enabled =
86 tegra_platform_is_silicon() ? platform->enable_aelpg : false;
87
88 /* set default values to aelpg parameters */
89 g->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US;
90 g->pmu.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US;
91 g->pmu.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US;
92 g->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US;
93 g->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT;
94}
95
96static void nvgpu_init_mm_vars(struct gk20a *g)
97{
98 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
99
100 g->mm.bypass_smmu = platform->bypass_smmu;
101 g->mm.disable_bigpage = platform->disable_bigpage;
102 g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem;
103}
104
105int nvgpu_probe(struct gk20a *g,
106 const char *debugfs_symlink,
107 const char *interface_name,
108 struct class *class)
109{
110 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
111 int err = 0;
112
113 nvgpu_init_vars(g);
114 nvgpu_init_timeout(g);
115 nvgpu_init_timeslice(g);
116 nvgpu_init_pm_vars(g);
117
118 err = gk20a_user_init(g->dev, interface_name, class);
119 if (err)
120 return err;
121
122 /* Initialize the platform interface. */
123 err = platform->probe(g->dev);
124 if (err) {
125 dev_err(g->dev, "platform probe failed");
126 return err;
127 }
128
129 /* Initialise scaling */
130 if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))
131 gk20a_scale_init(g->dev);
132
133 err = gk20a_secure_page_alloc(g->dev);
134 if (err)
135 dev_err(g->dev,
136 "failed to allocate secure buffer %d\n", err);
137
138 if (platform->late_probe) {
139 err = platform->late_probe(g->dev);
140 if (err) {
141 dev_err(g->dev, "late probe failed");
142 return err;
143 }
144 }
145
146 nvgpu_init_mm_vars(g);
147
148 gk20a_create_sysfs(g->dev);
149 gk20a_debug_init(g->dev, debugfs_symlink);
150
151 g->remove_support = gk20a_remove_support;
152
153 return 0;
154}
diff --git a/drivers/gpu/nvgpu/nvgpu_common.h b/drivers/gpu/nvgpu/nvgpu_common.h
new file mode 100644
index 00000000..c9914089
--- /dev/null
+++ b/drivers/gpu/nvgpu/nvgpu_common.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef NVGPU_COMMON_H
18#define NVGPU_COMMON_H
19
20struct gk20a;
21
22int nvgpu_probe(struct gk20a *g,
23 const char *debugfs_symlink,
24 const char *interface_name,
25 struct class *class);
26
27#endif
diff --git a/drivers/gpu/nvgpu/pci.c b/drivers/gpu/nvgpu/pci.c
index cbf444ad..a67bbd54 100644
--- a/drivers/gpu/nvgpu/pci.c
+++ b/drivers/gpu/nvgpu/pci.c
@@ -18,6 +18,7 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/pm_runtime.h> 19#include <linux/pm_runtime.h>
20#include "pci.h" 20#include "pci.h"
21#include "nvgpu_common.h"
21#include "gk20a/gk20a.h" 22#include "gk20a/gk20a.h"
22#include "gk20a/platform_gk20a.h" 23#include "gk20a/platform_gk20a.h"
23 24
@@ -58,6 +59,8 @@ static struct gk20a_platform nvgpu_pci_device = {
58 .ch_wdt_timeout_ms = 7000, 59 .ch_wdt_timeout_ms = 7000,
59 60
60 .has_ce = true, 61 .has_ce = true,
62
63 .vidmem_is_vidmem = true,
61}; 64};
62 65
63static struct pci_device_id nvgpu_pci_table[] = { 66static struct pci_device_id nvgpu_pci_table[] = {
@@ -113,19 +116,9 @@ static int nvgpu_pci_init_support(struct pci_dev *pdev)
113 goto fail; 116 goto fail;
114 } 117 }
115 118
116 g->regs_saved = g->regs;
117 g->bar1_saved = g->bar1;
118
119 mutex_init(&g->dbg_sessions_lock);
120 mutex_init(&g->client_lock);
121 mutex_init(&g->ch_wdt_lock);
122 mutex_init(&g->poweroff_lock);
123
124 g->remove_support = gk20a_remove_support;
125 return 0; 119 return 0;
126 120
127 fail: 121 fail:
128 gk20a_remove_support(&pdev->dev);
129 return err; 122 return err;
130} 123}
131 124
@@ -200,9 +193,6 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
200 return -ENOMEM; 193 return -ENOMEM;
201 } 194 }
202 195
203 init_waitqueue_head(&g->sw_irq_stall_last_handled_wq);
204 init_waitqueue_head(&g->sw_irq_nonstall_last_handled_wq);
205
206 platform->g = g; 196 platform->g = g;
207 g->dev = &pdev->dev; 197 g->dev = &pdev->dev;
208 198
@@ -215,6 +205,7 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
215 g->irq_nonstall = pdev->irq; 205 g->irq_nonstall = pdev->irq;
216 if (g->irq_stall < 0) 206 if (g->irq_stall < 0)
217 return -ENXIO; 207 return -ENXIO;
208
218 err = devm_request_threaded_irq(&pdev->dev, 209 err = devm_request_threaded_irq(&pdev->dev,
219 g->irq_stall, 210 g->irq_stall,
220 nvgpu_pci_isr, 211 nvgpu_pci_isr,
@@ -227,6 +218,10 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
227 } 218 }
228 disable_irq(g->irq_stall); 219 disable_irq(g->irq_stall);
229 220
221 err = nvgpu_pci_init_support(pdev);
222 if (err)
223 return err;
224
230 if (strchr(dev_name(&pdev->dev), '%')) { 225 if (strchr(dev_name(&pdev->dev), '%')) {
231 gk20a_err(&pdev->dev, "illegal character in device name"); 226 gk20a_err(&pdev->dev, "illegal character in device name");
232 return -EINVAL; 227 return -EINVAL;
@@ -236,57 +231,12 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
236 if (!nodefmt) 231 if (!nodefmt)
237 return -ENOMEM; 232 return -ENOMEM;
238 233
239 err = gk20a_user_init(&pdev->dev, nodefmt, &nvgpu_pci_class); 234 err = nvgpu_probe(g, "gpu_pci", nodefmt, &nvgpu_pci_class);
240 kfree(nodefmt);
241 nodefmt = NULL;
242 if (err)
243 return err;
244
245 err = nvgpu_pci_init_support(pdev);
246 if (err) 235 if (err)
247 return err; 236 return err;
248 237
249 init_rwsem(&g->busy_lock); 238 kfree(nodefmt);
250 mutex_init(&platform->railgate_lock); 239 nodefmt = NULL;
251
252 spin_lock_init(&g->mc_enable_lock);
253
254 gk20a_debug_init(&pdev->dev);
255
256 /* Initialize the platform interface. */
257 err = platform->probe(&pdev->dev);
258 if (err) {
259 gk20a_err(&pdev->dev, "platform probe failed");
260 return err;
261 }
262
263 /* Set DMA parameters to allow larger sgt lists */
264 pdev->dev.dma_parms = &g->dma_parms;
265 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
266
267 g->gr_idle_timeout_default =
268 CONFIG_GK20A_DEFAULT_TIMEOUT;
269 if (tegra_platform_is_silicon())
270 g->timeouts_enabled = true;
271
272 g->runlist_interleave = true;
273
274 g->timeslice_low_priority_us = 1300;
275 g->timeslice_medium_priority_us = 2600;
276 g->timeslice_high_priority_us = 5200;
277
278 gk20a_create_sysfs(&pdev->dev);
279
280 g->mm.has_physical_mode = false;
281 g->mm.vidmem_is_vidmem = true;
282#ifdef CONFIG_DEBUG_FS
283 g->mm.ltc_enabled = true;
284 g->mm.ltc_enabled_debug = true;
285#endif
286 g->mm.bypass_smmu = platform->bypass_smmu;
287 g->mm.disable_bigpage = platform->disable_bigpage;
288
289 gk20a_init_gr(g);
290 240
291 err = nvgpu_pci_pm_init(&pdev->dev); 241 err = nvgpu_pci_pm_init(&pdev->dev);
292 if (err) { 242 if (err) {
@@ -294,6 +244,8 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
294 return err; 244 return err;
295 } 245 }
296 246
247 g->mm.has_physical_mode = false;
248
297 return 0; 249 return 0;
298} 250}
299 251
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c
index c548175a..27d98eb8 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.c
@@ -599,7 +599,7 @@ int vgpu_probe(struct platform_device *pdev)
599 if (IS_ERR(priv->intr_handler)) 599 if (IS_ERR(priv->intr_handler))
600 return -ENOMEM; 600 return -ENOMEM;
601 601
602 gk20a_debug_init(dev); 602 gk20a_debug_init(dev, "gpu.0");
603 603
604 /* Set DMA parameters to allow larger sgt lists */ 604 /* Set DMA parameters to allow larger sgt lists */
605 dev->dma_parms = &gk20a->dma_parms; 605 dev->dma_parms = &gk20a->dma_parms;