gpu: nvgpu: gv11b: sw methods for shader exception

Added proper sw methods handling of shader execptions
for gv11b.

Bug 1834201

Change-Id: I3f3a45beed777cc4af59368dccd9dc7bb8181c37
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1283729
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 32 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 4984af46..79eee0e5 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -407,6 +407,25 @@ static void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data)
         gk20a_dbg_fn("done");
 }
 
+
+static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data)
+{
+        u32 val;
+
+        gk20a_dbg_fn("");
+
+        if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE)
+                val = 0;
+        else
+                val = 0xffffffff;
+
+        /* setup sm warp esr report masks */
+        gk20a_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(), val);
+
+        /* setup sm global esr report mask */
+        gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(), val);
+}
+
 static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
                                      u32 class_num, u32 offset, u32 data)
 {
@@ -415,7 +434,7 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
         if (class_num == VOLTA_COMPUTE_A) {
                 switch (offset << 2) {
                 case NVC0C0_SET_SHADER_EXCEPTIONS:
-                        gk20a_gr_set_shader_exceptions(g, data);
+                        gv11b_gr_set_shader_exceptions(g, data);
                         break;
                 default:
                         goto fail;
@@ -425,7 +444,7 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
         if (class_num == VOLTA_A) {
                 switch (offset << 2) {
                 case NVC397_SET_SHADER_EXCEPTIONS:
-                        gk20a_gr_set_shader_exceptions(g, data);
+                        gv11b_gr_set_shader_exceptions(g, data);
                         break;
                 case NVC397_SET_CIRCULAR_BUFFER_SIZE:
                         g->ops.gr.set_circular_buffer_size(g, data);
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index d31c92ca..b2549edd 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -43,6 +43,8 @@ enum {
 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE   0x02dc
 #define NVC397_SET_GO_IDLE_TIMEOUT              0x022c
 
+#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
+
 void gv11b_init_gr(struct gpu_ops *ops);
 int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size,
                         struct mem_desc *mem);
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
index 99da5f73..656597ba 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -554,6 +554,14 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void)
 {
         return 0x80000000;
 }
+static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00419ea8;
+}
+static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void)
+{
+        return 0x00419eac;
+}
 static inline u32 gr_fe_go_idle_timeout_r(void)
 {
         return 0x00404154;