diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2015-11-25 04:52:24 -0500 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-11-30 11:48:59 -0500 |
commit | 632a86f7cdec9f795fdef56ad028694c72d4e9d4 (patch) | |
tree | f3effaac4d6347614154d1c483eceaa3c0480647 /drivers/gpu/nvgpu | |
parent | c45f8cadee552001ac6881ef570730055a98a7c5 (diff) |
gpu: nvgpu: IOCTL to disable watchdog per-channel
Add IOCTL NVGPU_IOCTL_CHANNEL_WDT to disable/enable
watchdog per-channel
Also, if watchdog is disabled, we currently schedule
the worker with MAX timeout.
Instead of this, do not schedule any worker if
watchdog is disabled
Bug 1683059
Bug 1700277
Change-Id: I7f6bec84adeedb74e014ed6d1471317b854df84c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/837962
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 |
4 files changed, 26 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 5f9711d3..99cfb07e 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -630,6 +630,17 @@ static int gk20a_channel_cycle_stats_snapshot(struct channel_gk20a *ch, | |||
630 | } | 630 | } |
631 | #endif | 631 | #endif |
632 | 632 | ||
633 | static int gk20a_channel_set_wdt_status(struct channel_gk20a *ch, | ||
634 | struct nvgpu_channel_wdt_args *args) | ||
635 | { | ||
636 | if (args->wdt_status == NVGPU_IOCTL_CHANNEL_DISABLE_WDT) | ||
637 | ch->wdt_enabled = false; | ||
638 | else if (args->wdt_status == NVGPU_IOCTL_CHANNEL_ENABLE_WDT) | ||
639 | ch->wdt_enabled = true; | ||
640 | |||
641 | return 0; | ||
642 | } | ||
643 | |||
633 | static int gk20a_init_error_notifier(struct channel_gk20a *ch, | 644 | static int gk20a_init_error_notifier(struct channel_gk20a *ch, |
634 | struct nvgpu_set_error_notifier *args) { | 645 | struct nvgpu_set_error_notifier *args) { |
635 | void *va; | 646 | void *va; |
@@ -1424,12 +1435,7 @@ bool gk20a_channel_update_and_check_timeout(struct channel_gk20a *ch, | |||
1424 | static u32 gk20a_get_channel_watchdog_timeout(struct channel_gk20a *ch) | 1435 | static u32 gk20a_get_channel_watchdog_timeout(struct channel_gk20a *ch) |
1425 | { | 1436 | { |
1426 | struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev); | 1437 | struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev); |
1427 | 1438 | return platform->ch_wdt_timeout_ms; | |
1428 | if (ch->g->timeouts_enabled && ch->g->ch_wdt_enabled && | ||
1429 | platform->ch_wdt_timeout_ms) | ||
1430 | return platform->ch_wdt_timeout_ms; | ||
1431 | else | ||
1432 | return (u32)MAX_SCHEDULE_TIMEOUT; | ||
1433 | } | 1439 | } |
1434 | 1440 | ||
1435 | static u32 get_gp_free_count(struct channel_gk20a *c) | 1441 | static u32 get_gp_free_count(struct channel_gk20a *c) |
@@ -1519,6 +1525,14 @@ static void trace_write_pushbuffer_range(struct channel_gk20a *c, | |||
1519 | static void gk20a_channel_timeout_start(struct channel_gk20a *ch, | 1525 | static void gk20a_channel_timeout_start(struct channel_gk20a *ch, |
1520 | struct channel_gk20a_job *job) | 1526 | struct channel_gk20a_job *job) |
1521 | { | 1527 | { |
1528 | struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev); | ||
1529 | |||
1530 | if (!ch->g->timeouts_enabled || !platform->ch_wdt_timeout_ms) | ||
1531 | return; | ||
1532 | |||
1533 | if (!ch->wdt_enabled) | ||
1534 | return; | ||
1535 | |||
1522 | mutex_lock(&ch->timeout.lock); | 1536 | mutex_lock(&ch->timeout.lock); |
1523 | 1537 | ||
1524 | if (ch->timeout.initialized) { | 1538 | if (ch->timeout.initialized) { |
@@ -2117,6 +2131,7 @@ int gk20a_init_channel_support(struct gk20a *g, u32 chid) | |||
2117 | c->g = NULL; | 2131 | c->g = NULL; |
2118 | c->hw_chid = chid; | 2132 | c->hw_chid = chid; |
2119 | c->bound = false; | 2133 | c->bound = false; |
2134 | c->wdt_enabled = true; | ||
2120 | spin_lock_init(&c->ref_obtain_lock); | 2135 | spin_lock_init(&c->ref_obtain_lock); |
2121 | atomic_set(&c->ref_count, 0); | 2136 | atomic_set(&c->ref_count, 0); |
2122 | c->referenceable = false; | 2137 | c->referenceable = false; |
@@ -2839,6 +2854,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
2839 | gk20a_idle(dev); | 2854 | gk20a_idle(dev); |
2840 | break; | 2855 | break; |
2841 | #endif | 2856 | #endif |
2857 | case NVGPU_IOCTL_CHANNEL_WDT: | ||
2858 | err = gk20a_channel_set_wdt_status(ch, | ||
2859 | (struct nvgpu_channel_wdt_args *)buf); | ||
2860 | break; | ||
2842 | default: | 2861 | default: |
2843 | dev_dbg(&dev->dev, "unrecognized ioctl cmd: 0x%x", cmd); | 2862 | dev_dbg(&dev->dev, "unrecognized ioctl cmd: 0x%x", cmd); |
2844 | err = -ENOTTY; | 2863 | err = -ENOTTY; |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 245db56a..55528dd9 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -92,6 +92,7 @@ struct channel_gk20a { | |||
92 | wait_queue_head_t ref_count_dec_wq; | 92 | wait_queue_head_t ref_count_dec_wq; |
93 | 93 | ||
94 | int hw_chid; | 94 | int hw_chid; |
95 | bool wdt_enabled; | ||
95 | bool bound; | 96 | bool bound; |
96 | bool first_init; | 97 | bool first_init; |
97 | bool vpr; | 98 | bool vpr; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 79218c97..9bbc9bd8 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1436,7 +1436,6 @@ static int gk20a_probe(struct platform_device *dev) | |||
1436 | CONFIG_GK20A_DEFAULT_TIMEOUT; | 1436 | CONFIG_GK20A_DEFAULT_TIMEOUT; |
1437 | if (tegra_platform_is_silicon()) | 1437 | if (tegra_platform_is_silicon()) |
1438 | gk20a->timeouts_enabled = true; | 1438 | gk20a->timeouts_enabled = true; |
1439 | gk20a->ch_wdt_enabled = true; | ||
1440 | 1439 | ||
1441 | gk20a->timeslice_low_priority_us = 1300; | 1440 | gk20a->timeslice_low_priority_us = 1300; |
1442 | gk20a->timeslice_medium_priority_us = 2600; | 1441 | gk20a->timeslice_medium_priority_us = 2600; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index fe51f356..51955a3a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -499,7 +499,6 @@ struct gk20a { | |||
499 | u32 gr_idle_timeout_default; | 499 | u32 gr_idle_timeout_default; |
500 | u32 timeouts_enabled; | 500 | u32 timeouts_enabled; |
501 | 501 | ||
502 | u32 ch_wdt_enabled; | ||
503 | struct mutex ch_wdt_lock; | 502 | struct mutex ch_wdt_lock; |
504 | 503 | ||
505 | /* Channel priorities */ | 504 | /* Channel priorities */ |