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authorAlex Waterman <alexw@nvidia.com>2017-06-08 18:05:19 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-04 17:54:26 -0400
commit5a5792d911d99a08663c59f74c552883804780f3 (patch)
tree9805d88980e8dcce78d9c0b353687f1b43d7a66c /drivers/gpu/nvgpu
parent3e3c1920404ddec1ddbcf8adad93067f384a3e59 (diff)
gpu: nvgpu: Remove mm.get_iova_addr
Volta changes for equivalent change on nvgpu. JIRA NVGPU-30 Change-Id: I78e84ce67468dfe3556232ddb25e824f6b84835c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530863 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fb_gv11b.c4
-rw-r--r--drivers/gpu/nvgpu/gv11b/mm_gv11b.c7
-rw-r--r--drivers/gpu/nvgpu/gv11b/subctx_gv11b.c3
3 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
index fd63e9ff..51ee55f8 100644
--- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
@@ -101,8 +101,8 @@ static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
101 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) 101 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
102 compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); 102 compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem);
103 else 103 else
104 compbit_store_iova = g->ops.mm.get_iova_addr(g, 104 compbit_store_iova = nvgpu_mem_get_addr(g,
105 gr->compbit_store.mem.priv.sgt->sgl, 0); 105 &gr->compbit_store.mem);
106 106
107 compbit_base_post_divide64 = compbit_store_iova >> 107 compbit_base_post_divide64 = compbit_store_iova >>
108 fb_mmu_cbc_base_address_alignment_shift_v(); 108 fb_mmu_cbc_base_address_alignment_shift_v();
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
index 9be8352a..7ba8f74f 100644
--- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
@@ -260,10 +260,10 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate)
260 * checking bit 36 of the phsyical address. So if a mapping should allocte lines 260 * checking bit 36 of the phsyical address. So if a mapping should allocte lines
261 * in the L3 this bit must be set. 261 * in the L3 this bit must be set.
262 */ 262 */
263u64 gv11b_gpu_phys_addr(struct gk20a *g, 263static u64 gv11b_gpu_phys_addr(struct gk20a *g,
264 struct nvgpu_gmmu_attrs *attrs, u64 phys) 264 struct nvgpu_gmmu_attrs *attrs, u64 phys)
265{ 265{
266 if (attrs->t19x_attrs.l3_alloc) 266 if (attrs && attrs->t19x_attrs.l3_alloc)
267 return phys | NVGPU_L3_ALLOC_BIT; 267 return phys | NVGPU_L3_ALLOC_BIT;
268 268
269 return phys; 269 return phys;
@@ -322,6 +322,7 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g)
322void gv11b_init_mm(struct gpu_ops *gops) 322void gv11b_init_mm(struct gpu_ops *gops)
323{ 323{
324 gp10b_init_mm(gops); 324 gp10b_init_mm(gops);
325 gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr;
325 gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; 326 gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported;
326 gops->mm.init_inst_block = gv11b_init_inst_block; 327 gops->mm.init_inst_block = gv11b_init_inst_block;
327 gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; 328 gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending;
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
index bda36216..72a66530 100644
--- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
@@ -143,13 +143,14 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c,
143 struct nvgpu_mem *inst_block) 143 struct nvgpu_mem *inst_block)
144{ 144{
145 struct gk20a *g = c->g; 145 struct gk20a *g = c->g;
146 struct vm_gk20a *vm = c->vm;
146 u32 lo, hi; 147 u32 lo, hi;
147 u32 subctx_id = 0; 148 u32 subctx_id = 0;
148 u32 format_word; 149 u32 format_word;
149 u32 pdb_addr_lo, pdb_addr_hi; 150 u32 pdb_addr_lo, pdb_addr_hi;
150 u64 pdb_addr; 151 u64 pdb_addr;
151 152
152 pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem->priv.sgt->sgl, 0); 153 pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem);
153 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); 154 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
154 pdb_addr_hi = u64_hi32(pdb_addr); 155 pdb_addr_hi = u64_hi32(pdb_addr);
155 format_word = ram_in_sc_page_dir_base_target_f( 156 format_word = ram_in_sc_page_dir_base_target_f(