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authorSeema Khowala <seemaj@nvidia.com>2017-06-20 15:25:05 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-21 18:24:54 -0400
commit581e8b4ec86b13706e4423609a543fc2510b4ffe (patch)
tree0f0bde7965de6839baa44813f7f01536d179985b /drivers/gpu/nvgpu
parent8ca81687c7746048d1465a82ca81e826285fe3f1 (diff)
gpu: nvgpu: check ctx valid bit at right place
When contexts are unloaded from GR, the valid bit is reset but the instance pointer information remains intact. Check valid bit in *is_channel_ctx_resident* function as valid bit might not be set when *get_channel_from_ctx function* is called from gr_isr Bug 200289491 Change-Id: I4da7f04794c7e7e80b511756dbd851205cd76fbc Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1505908 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c24
1 files changed, 17 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 4219e841..2afa79f1 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5906,11 +5906,10 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx(
5906 struct channel_gk20a *ret = NULL; 5906 struct channel_gk20a *ret = NULL;
5907 5907
5908 /* when contexts are unloaded from GR, the valid bit is reset 5908 /* when contexts are unloaded from GR, the valid bit is reset
5909 * but the instance pointer information remains intact. So the 5909 * but the instance pointer information remains intact.
5910 * valid bit must be checked to be absolutely certain that a 5910 * This might be called from gr_isr where contexts might be
5911 * valid context is currently resident. */ 5911 * unloaded. No need to check ctx_valid bit
5912 if (!gr_fecs_current_ctx_valid_v(curr_ctx)) 5912 */
5913 return NULL;
5914 5913
5915 nvgpu_spinlock_acquire(&gr->ch_tlb_lock); 5914 nvgpu_spinlock_acquire(&gr->ch_tlb_lock);
5916 5915
@@ -6475,10 +6474,12 @@ int gk20a_gr_isr(struct gk20a *g)
6475 isr_data.class_num = gr_fe_object_table_nvclass_v(obj_table); 6474 isr_data.class_num = gr_fe_object_table_nvclass_v(obj_table);
6476 6475
6477 ch = gk20a_gr_get_channel_from_ctx(g, isr_data.curr_ctx, &tsgid); 6476 ch = gk20a_gr_get_channel_from_ctx(g, isr_data.curr_ctx, &tsgid);
6478 if (ch) 6477 if (ch) {
6479 isr_data.chid = ch->hw_chid; 6478 isr_data.chid = ch->hw_chid;
6480 else 6479 } else {
6481 isr_data.chid = FIFO_INVAL_CHANNEL_ID; 6480 isr_data.chid = FIFO_INVAL_CHANNEL_ID;
6481 nvgpu_err(g, "ch id is INVALID 0xffffffff");
6482 }
6482 6483
6483 gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, 6484 gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg,
6484 "channel %d: addr 0x%08x, " 6485 "channel %d: addr 0x%08x, "
@@ -8283,6 +8284,15 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch)
8283 bool ret = false; 8284 bool ret = false;
8284 8285
8285 curr_gr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r()); 8286 curr_gr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r());
8287
8288 /* when contexts are unloaded from GR, the valid bit is reset
8289 * but the instance pointer information remains intact. So the
8290 * valid bit must be checked to be absolutely certain that a
8291 * valid context is currently resident.
8292 */
8293 if (!gr_fecs_current_ctx_valid_v(curr_gr_ctx))
8294 return NULL;
8295
8286 curr_ch = gk20a_gr_get_channel_from_ctx(g, curr_gr_ctx, 8296 curr_ch = gk20a_gr_get_channel_from_ctx(g, curr_gr_ctx,
8287 &curr_gr_tsgid); 8297 &curr_gr_tsgid);
8288 8298