diff options
author | Peter Daifuku <pdaifuku@nvidia.com> | 2016-10-21 18:26:15 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-11-03 13:35:12 -0400 |
commit | 57821e215756b3df7acc9c0eb5017e39f141d381 (patch) | |
tree | 5cf4c54d54600b96fe9411278e823e55fb01398d /drivers/gpu/nvgpu | |
parent | 3ec909036af46fbe582c50e486beb2bded42b645 (diff) |
gpu: nvgpu: vgpu: alloc hwpm ctxt buf on client
In hypervisor mode, all GPU VA allocations must be done by client;
fix this for the allocation of the hwpm ctxt buffer
Bug 200231611
Change-Id: I0270b1298308383a969a47d0a859ed53c20594ef
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1240913
(cherry picked from commit 49314d42b13e27dc2f8c1e569a8c3e750173148d)
Reviewed-on: http://git-master/r/1245867
(cherry picked from commit d0b10e84d90d0fd61eca8be0f9e879d9cec71d3e)
Reviewed-on: http://git-master/r/1246700
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 39 |
2 files changed, 25 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 1a9bee5f..512d32e9 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -110,7 +110,6 @@ struct zcull_ctx_desc { | |||
110 | struct pm_ctx_desc { | 110 | struct pm_ctx_desc { |
111 | struct mem_desc mem; | 111 | struct mem_desc mem; |
112 | u32 pm_mode; | 112 | u32 pm_mode; |
113 | bool ctx_was_enabled; /* Used in the virtual case only */ | ||
114 | }; | 113 | }; |
115 | 114 | ||
116 | struct gk20a; | 115 | struct gk20a; |
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 89223091..654b3ca3 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -91,8 +91,10 @@ int vgpu_gr_init_ctx_state(struct gk20a *g) | |||
91 | 91 | ||
92 | g->gr.ctx_vars.golden_image_size = priv->constants.golden_ctx_size; | 92 | g->gr.ctx_vars.golden_image_size = priv->constants.golden_ctx_size; |
93 | g->gr.ctx_vars.zcull_ctxsw_image_size = priv->constants.zcull_ctx_size; | 93 | g->gr.ctx_vars.zcull_ctxsw_image_size = priv->constants.zcull_ctx_size; |
94 | g->gr.ctx_vars.pm_ctxsw_image_size = priv->constants.hwpm_ctx_size; | ||
94 | if (!g->gr.ctx_vars.golden_image_size || | 95 | if (!g->gr.ctx_vars.golden_image_size || |
95 | !g->gr.ctx_vars.zcull_ctxsw_image_size) | 96 | !g->gr.ctx_vars.zcull_ctxsw_image_size || |
97 | !g->gr.ctx_vars.pm_ctxsw_image_size) | ||
96 | return -ENXIO; | 98 | return -ENXIO; |
97 | 99 | ||
98 | gr->ctx_vars.buffer_size = g->gr.ctx_vars.golden_image_size; | 100 | gr->ctx_vars.buffer_size = g->gr.ctx_vars.golden_image_size; |
@@ -390,12 +392,13 @@ static void vgpu_gr_free_channel_pm_ctx(struct channel_gk20a *c) | |||
390 | struct tegra_vgpu_cmd_msg msg; | 392 | struct tegra_vgpu_cmd_msg msg; |
391 | struct tegra_vgpu_channel_free_hwpm_ctx *p = &msg.params.free_hwpm_ctx; | 393 | struct tegra_vgpu_channel_free_hwpm_ctx *p = &msg.params.free_hwpm_ctx; |
392 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | 394 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
395 | struct pm_ctx_desc *pm_ctx = &ch_ctx->pm_ctx; | ||
393 | int err; | 396 | int err; |
394 | 397 | ||
395 | gk20a_dbg_fn(""); | 398 | gk20a_dbg_fn(""); |
396 | 399 | ||
397 | /* check if hwpm was ever initialized. If not, nothing to do */ | 400 | /* check if hwpm was ever initialized. If not, nothing to do */ |
398 | if (ch_ctx->pm_ctx.ctx_was_enabled == false) | 401 | if (pm_ctx->mem.gpu_va == 0) |
399 | return; | 402 | return; |
400 | 403 | ||
401 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX; | 404 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX; |
@@ -404,7 +407,8 @@ static void vgpu_gr_free_channel_pm_ctx(struct channel_gk20a *c) | |||
404 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 407 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
405 | WARN_ON(err || msg.ret); | 408 | WARN_ON(err || msg.ret); |
406 | 409 | ||
407 | ch_ctx->pm_ctx.ctx_was_enabled = false; | 410 | gk20a_vm_free_va(c->vm, pm_ctx->mem.gpu_va, pm_ctx->mem.size, 0); |
411 | pm_ctx->mem.gpu_va = 0; | ||
408 | } | 412 | } |
409 | 413 | ||
410 | static void vgpu_gr_free_channel_ctx(struct channel_gk20a *c) | 414 | static void vgpu_gr_free_channel_ctx(struct channel_gk20a *c) |
@@ -1040,28 +1044,35 @@ static int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, | |||
1040 | static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, | 1044 | static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, |
1041 | struct channel_gk20a *ch, bool enable) | 1045 | struct channel_gk20a *ch, bool enable) |
1042 | { | 1046 | { |
1047 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; | ||
1048 | struct pm_ctx_desc *pm_ctx = &ch_ctx->pm_ctx; | ||
1043 | struct tegra_vgpu_cmd_msg msg; | 1049 | struct tegra_vgpu_cmd_msg msg; |
1044 | struct tegra_vgpu_channel_set_ctxsw_mode *p = &msg.params.set_ctxsw_mode; | 1050 | struct tegra_vgpu_channel_set_ctxsw_mode *p = &msg.params.set_ctxsw_mode; |
1045 | int err; | 1051 | int err; |
1046 | 1052 | ||
1047 | gk20a_dbg_fn(""); | 1053 | gk20a_dbg_fn(""); |
1048 | 1054 | ||
1049 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE; | ||
1050 | msg.handle = vgpu_get_handle(g); | ||
1051 | p->handle = ch->virt_ctx; | ||
1052 | |||
1053 | /* If we just enabled HWPM context switching, flag this | ||
1054 | * so we know we need to free the buffer when channel contexts | ||
1055 | * are cleaned up. | ||
1056 | */ | ||
1057 | if (enable) { | 1055 | if (enable) { |
1058 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; | ||
1059 | ch_ctx->pm_ctx.ctx_was_enabled = true; | ||
1060 | |||
1061 | p->mode = TEGRA_VGPU_CTXSW_MODE_CTXSW; | 1056 | p->mode = TEGRA_VGPU_CTXSW_MODE_CTXSW; |
1057 | |||
1058 | /* Allocate buffer if necessary */ | ||
1059 | if (pm_ctx->mem.gpu_va == 0) { | ||
1060 | pm_ctx->mem.gpu_va = gk20a_vm_alloc_va(ch->vm, | ||
1061 | g->gr.ctx_vars.pm_ctxsw_image_size, | ||
1062 | gmmu_page_size_kernel); | ||
1063 | |||
1064 | if (!pm_ctx->mem.gpu_va) | ||
1065 | return -ENOMEM; | ||
1066 | pm_ctx->mem.size = g->gr.ctx_vars.pm_ctxsw_image_size; | ||
1067 | } | ||
1062 | } else | 1068 | } else |
1063 | p->mode = TEGRA_VGPU_CTXSW_MODE_NO_CTXSW; | 1069 | p->mode = TEGRA_VGPU_CTXSW_MODE_NO_CTXSW; |
1064 | 1070 | ||
1071 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE; | ||
1072 | msg.handle = vgpu_get_handle(g); | ||
1073 | p->handle = ch->virt_ctx; | ||
1074 | p->gpu_va = pm_ctx->mem.gpu_va; | ||
1075 | |||
1065 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 1076 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
1066 | WARN_ON(err || msg.ret); | 1077 | WARN_ON(err || msg.ret); |
1067 | 1078 | ||