diff options
author | Alex Frid <afrid@nvidia.com> | 2014-08-25 23:36:02 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:03 -0400 |
commit | 55438f4009accdc0e113d1b82ade1521fa8be0b4 (patch) | |
tree | 70521eb5ae9911a8f1125acd4855be3585208d96 /drivers/gpu/nvgpu | |
parent | 4b02dea47d672baf6a566d187cb42c91bf14bf8c (diff) |
gpu: nvgpu: Re-factor GM20b clk_lock_gpc_pll_under_bypass()
Passed pll structure to GM20b clk_lock_gpc_pll_under_bypass() function
instead of individual M/N/PL dividers values.
Change-Id: I4881f6fad0e4be63a0eefb7277894d6900e9bb13
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/488024
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index bfc1cf55..f8b54465 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -283,7 +283,7 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) | |||
283 | return 0; | 283 | return 0; |
284 | } | 284 | } |
285 | 285 | ||
286 | static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, u32 m, u32 n, u32 pl) | 286 | static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll) |
287 | { | 287 | { |
288 | u32 data, cfg, coeff, timeout; | 288 | u32 data, cfg, coeff, timeout; |
289 | 289 | ||
@@ -316,9 +316,9 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, u32 m, u32 n, u32 pl) | |||
316 | } | 316 | } |
317 | 317 | ||
318 | /* change coefficients */ | 318 | /* change coefficients */ |
319 | coeff = trim_sys_gpcpll_coeff_mdiv_f(m) | | 319 | coeff = trim_sys_gpcpll_coeff_mdiv_f(gpll->M) | |
320 | trim_sys_gpcpll_coeff_ndiv_f(n) | | 320 | trim_sys_gpcpll_coeff_ndiv_f(gpll->N) | |
321 | trim_sys_gpcpll_coeff_pldiv_f(pl); | 321 | trim_sys_gpcpll_coeff_pldiv_f(gpll->PL); |
322 | gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff); | 322 | gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff); |
323 | 323 | ||
324 | /* enable PLL after changing coefficients */ | 324 | /* enable PLL after changing coefficients */ |
@@ -378,6 +378,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct pll *gpll_new, | |||
378 | u32 cfg, coeff; | 378 | u32 cfg, coeff; |
379 | u32 m, n, pl, nlo; | 379 | u32 m, n, pl, nlo; |
380 | bool can_slide; | 380 | bool can_slide; |
381 | struct pll gpll; | ||
381 | 382 | ||
382 | gk20a_dbg_fn(""); | 383 | gk20a_dbg_fn(""); |
383 | 384 | ||
@@ -443,15 +444,14 @@ static int clk_program_gpc_pll(struct gk20a *g, struct pll *gpll_new, | |||
443 | * is effectively NOP). PL is preserved (not set to target) of post | 444 | * is effectively NOP). PL is preserved (not set to target) of post |
444 | * divider is glitchless. Otherwise it is at PL target. | 445 | * divider is glitchless. Otherwise it is at PL target. |
445 | */ | 446 | */ |
446 | m = gpll_new->M; | 447 | gpll = *gpll_new; |
447 | nlo = DIV_ROUND_UP(m * gpc_pll_params.min_vco, gpll_new->clk_in); | 448 | if (allow_slide) |
448 | n = allow_slide ? nlo : gpll_new->N; | 449 | gpll.N = DIV_ROUND_UP(gpll_new->M * gpc_pll_params.min_vco, |
450 | gpll_new->clk_in); | ||
449 | #if PLDIV_GLITCHLESS | 451 | #if PLDIV_GLITCHLESS |
450 | pl = (gpll_new->PL < 2) ? 2 : gpll_new->PL; | 452 | gpll.PL = (gpll_new->PL < 2) ? 2 : gpll_new->PL; |
451 | #else | ||
452 | pl = gpll_new->PL; | ||
453 | #endif | 453 | #endif |
454 | clk_lock_gpc_pll_under_bypass(g, m, n, pl); | 454 | clk_lock_gpc_pll_under_bypass(g, &gpll); |
455 | gpll_new->enabled = true; | 455 | gpll_new->enabled = true; |
456 | 456 | ||
457 | #if PLDIV_GLITCHLESS | 457 | #if PLDIV_GLITCHLESS |