diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2017-07-05 03:07:23 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-18 14:04:23 -0400 |
commit | 5364257c7f9792b3e85d4af89528d6bda02bfee5 (patch) | |
tree | 12e7817b563605a8b6af63618048e0ec981261dc /drivers/gpu/nvgpu | |
parent | b1c95568823d8b7b19188de06c80b303e9c62f66 (diff) |
gpu : nvgpu: secure boot code unification.
This exposes all secure boot functions that can be
re-used by other chips. This is the first patch in
this series. Other pacthes will also follow.
JIRA NVGPU-60
Change-Id: I523637bbf601166f8a01ddf29a913e193d3fdc7a
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514567
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 79 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.h | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | 1 |
7 files changed, 69 insertions, 42 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index b1881827..ac195fea 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1134,6 +1134,7 @@ struct gk20a { | |||
1134 | u32 disable_syncpoints; | 1134 | u32 disable_syncpoints; |
1135 | 1135 | ||
1136 | bool support_pmu; | 1136 | bool support_pmu; |
1137 | u32 bootstrap_owner; | ||
1137 | 1138 | ||
1138 | bool is_virtual; | 1139 | bool is_virtual; |
1139 | 1140 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index e2f80307..2d8ed9ec 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -289,6 +289,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
289 | } | 289 | } |
290 | } | 290 | } |
291 | #endif | 291 | #endif |
292 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | ||
292 | gk20a_init_bus(gops); | 293 | gk20a_init_bus(gops); |
293 | gk20a_init_priv_ring(gops); | 294 | gk20a_init_priv_ring(gops); |
294 | gm20b_init_gr(gops); | 295 | gm20b_init_gr(gops); |
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 076c8829..dce297bd 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -35,6 +35,10 @@ | |||
35 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> | 35 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> |
36 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | 36 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> |
37 | 37 | ||
38 | #ifdef CONFIG_TEGRA_19x_GPU | ||
39 | #include "nvgpu_gpuid_t19x.h" | ||
40 | #endif | ||
41 | |||
38 | /*Defines*/ | 42 | /*Defines*/ |
39 | #define gp106_dbg_pmu(fmt, arg...) \ | 43 | #define gp106_dbg_pmu(fmt, arg...) \ |
40 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 44 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
@@ -51,30 +55,8 @@ typedef int (*get_ucode_details)(struct gk20a *g, | |||
51 | /*Externs*/ | 55 | /*Externs*/ |
52 | 56 | ||
53 | /*Forwards*/ | 57 | /*Forwards*/ |
54 | static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img); | ||
55 | static int fecs_ucode_details(struct gk20a *g, | ||
56 | struct flcn_ucode_img_v1 *p_img); | ||
57 | static int gpccs_ucode_details(struct gk20a *g, | ||
58 | struct flcn_ucode_img_v1 *p_img); | ||
59 | static int gp106_bootstrap_hs_flcn(struct gk20a *g); | 58 | static int gp106_bootstrap_hs_flcn(struct gk20a *g); |
60 | 59 | ||
61 | static int lsfm_discover_ucode_images(struct gk20a *g, | ||
62 | struct ls_flcn_mgr_v1 *plsfm); | ||
63 | static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, | ||
64 | struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id); | ||
65 | static void lsfm_free_ucode_img_res(struct gk20a *g, | ||
66 | struct flcn_ucode_img_v1 *p_img); | ||
67 | static void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g, | ||
68 | struct flcn_ucode_img_v1 *p_img); | ||
69 | static int lsf_gen_wpr_requirements(struct gk20a *g, | ||
70 | struct ls_flcn_mgr_v1 *plsfm); | ||
71 | static void lsfm_init_wpr_contents(struct gk20a *g, | ||
72 | struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *nonwpr); | ||
73 | static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm); | ||
74 | static int gp106_pmu_populate_loader_cfg(struct gk20a *g, | ||
75 | void *lsfm, u32 *p_bl_gen_desc_size); | ||
76 | static int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g, | ||
77 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); | ||
78 | static int gp106_prepare_ucode_blob(struct gk20a *g); | 60 | static int gp106_prepare_ucode_blob(struct gk20a *g); |
79 | 61 | ||
80 | /*Globals*/ | 62 | /*Globals*/ |
@@ -138,7 +120,7 @@ void gp106_init_secure_pmu(struct gpu_ops *gops) | |||
138 | } | 120 | } |
139 | /* TODO - check if any free blob res needed*/ | 121 | /* TODO - check if any free blob res needed*/ |
140 | 122 | ||
141 | static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | 123 | int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) |
142 | { | 124 | { |
143 | struct nvgpu_firmware *pmu_fw, *pmu_desc, *pmu_sig; | 125 | struct nvgpu_firmware *pmu_fw, *pmu_desc, *pmu_sig; |
144 | struct nvgpu_pmu *pmu = &g->pmu; | 126 | struct nvgpu_pmu *pmu = &g->pmu; |
@@ -208,7 +190,7 @@ release_img_fw: | |||
208 | return err; | 190 | return err; |
209 | } | 191 | } |
210 | 192 | ||
211 | static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | 193 | int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) |
212 | { | 194 | { |
213 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; | 195 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; |
214 | struct lsf_ucode_desc_v1 *lsf_desc; | 196 | struct lsf_ucode_desc_v1 *lsf_desc; |
@@ -226,6 +208,12 @@ static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
226 | GP106_FECS_UCODE_SIG, | 208 | GP106_FECS_UCODE_SIG, |
227 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | 209 | NVGPU_REQUEST_FIRMWARE_NO_SOC); |
228 | break; | 210 | break; |
211 | #if defined(CONFIG_TEGRA_19x_GPU) | ||
212 | case TEGRA_19x_GPUID: | ||
213 | fecs_sig = nvgpu_request_firmware(g, | ||
214 | GM20B_FECS_UCODE_SIG, 0); | ||
215 | break; | ||
216 | #endif | ||
229 | default: | 217 | default: |
230 | nvgpu_err(g, "no support for GPUID %x", ver); | 218 | nvgpu_err(g, "no support for GPUID %x", ver); |
231 | } | 219 | } |
@@ -291,7 +279,7 @@ rel_sig: | |||
291 | return err; | 279 | return err; |
292 | } | 280 | } |
293 | 281 | ||
294 | static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | 282 | int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) |
295 | { | 283 | { |
296 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; | 284 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; |
297 | struct lsf_ucode_desc_v1 *lsf_desc; | 285 | struct lsf_ucode_desc_v1 *lsf_desc; |
@@ -312,6 +300,12 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
312 | GP106_GPCCS_UCODE_SIG, | 300 | GP106_GPCCS_UCODE_SIG, |
313 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | 301 | NVGPU_REQUEST_FIRMWARE_NO_SOC); |
314 | break; | 302 | break; |
303 | #if defined(CONFIG_TEGRA_19x_GPU) | ||
304 | case TEGRA_19x_GPUID: | ||
305 | gpccs_sig = nvgpu_request_firmware(g, | ||
306 | T18x_GPCCS_UCODE_SIG, 0); | ||
307 | break; | ||
308 | #endif | ||
315 | default: | 309 | default: |
316 | nvgpu_err(g, "no support for GPUID %x", ver); | 310 | nvgpu_err(g, "no support for GPUID %x", ver); |
317 | } | 311 | } |
@@ -443,7 +437,7 @@ static u8 lsfm_falcon_disabled(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, | |||
443 | } | 437 | } |
444 | 438 | ||
445 | /* Discover all managed falcon ucode images */ | 439 | /* Discover all managed falcon ucode images */ |
446 | static int lsfm_discover_ucode_images(struct gk20a *g, | 440 | int lsfm_discover_ucode_images(struct gk20a *g, |
447 | struct ls_flcn_mgr_v1 *plsfm) | 441 | struct ls_flcn_mgr_v1 *plsfm) |
448 | { | 442 | { |
449 | struct nvgpu_pmu *pmu = &g->pmu; | 443 | struct nvgpu_pmu *pmu = &g->pmu; |
@@ -528,7 +522,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g, | |||
528 | return 0; | 522 | return 0; |
529 | } | 523 | } |
530 | 524 | ||
531 | static int gp106_pmu_populate_loader_cfg(struct gk20a *g, | 525 | int gp106_pmu_populate_loader_cfg(struct gk20a *g, |
532 | void *lsfm, u32 *p_bl_gen_desc_size) | 526 | void *lsfm, u32 *p_bl_gen_desc_size) |
533 | { | 527 | { |
534 | struct wpr_carveout_info wpr_inf; | 528 | struct wpr_carveout_info wpr_inf; |
@@ -601,7 +595,7 @@ static int gp106_pmu_populate_loader_cfg(struct gk20a *g, | |||
601 | return 0; | 595 | return 0; |
602 | } | 596 | } |
603 | 597 | ||
604 | static int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g, | 598 | int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g, |
605 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid) | 599 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid) |
606 | { | 600 | { |
607 | struct wpr_carveout_info wpr_inf; | 601 | struct wpr_carveout_info wpr_inf; |
@@ -629,7 +623,10 @@ static int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
629 | */ | 623 | */ |
630 | addr_base = p_lsfm->lsb_header.ucode_off; | 624 | addr_base = p_lsfm->lsb_header.ucode_off; |
631 | g->ops.pmu.get_wpr(g, &wpr_inf); | 625 | g->ops.pmu.get_wpr(g, &wpr_inf); |
632 | addr_base += (wpr_inf.wpr_base); | 626 | if (falconid == LSF_FALCON_ID_GPCCS) |
627 | addr_base += g->pmu.wpr_buf.gpu_va; | ||
628 | else | ||
629 | addr_base += wpr_inf.wpr_base; | ||
633 | 630 | ||
634 | gp106_dbg_pmu("gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, | 631 | gp106_dbg_pmu("gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, |
635 | p_lsfm->wpr_header.falcon_id); | 632 | p_lsfm->wpr_header.falcon_id); |
@@ -658,7 +655,7 @@ static int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
658 | } | 655 | } |
659 | 656 | ||
660 | /* Populate falcon boot loader generic desc.*/ | 657 | /* Populate falcon boot loader generic desc.*/ |
661 | static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | 658 | int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, |
662 | struct lsfm_managed_ucode_img_v2 *pnode) | 659 | struct lsfm_managed_ucode_img_v2 *pnode) |
663 | { | 660 | { |
664 | 661 | ||
@@ -683,7 +680,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | |||
683 | } | 680 | } |
684 | 681 | ||
685 | /* Initialize WPR contents */ | 682 | /* Initialize WPR contents */ |
686 | static void lsfm_init_wpr_contents(struct gk20a *g, | 683 | void lsfm_init_wpr_contents(struct gk20a *g, |
687 | struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode) | 684 | struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode) |
688 | { | 685 | { |
689 | struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list; | 686 | struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list; |
@@ -765,9 +762,9 @@ static void lsfm_init_wpr_contents(struct gk20a *g, | |||
765 | 762 | ||
766 | /* Tag the terminator WPR header with an invalid falcon ID. */ | 763 | /* Tag the terminator WPR header with an invalid falcon ID. */ |
767 | nvgpu_mem_wr32(g, ucode, | 764 | nvgpu_mem_wr32(g, ucode, |
768 | plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header) + | 765 | plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header_v1) + |
769 | offsetof(struct lsf_wpr_header, falcon_id), | 766 | offsetof(struct lsf_wpr_header_v1, falcon_id), |
770 | LSF_FALCON_ID_INVALID); | 767 | LSF_FALCON_ID_INVALID); |
771 | } | 768 | } |
772 | 769 | ||
773 | /*! | 770 | /*! |
@@ -815,7 +812,7 @@ static int lsfm_parse_no_loader_ucode(u32 *p_ucodehdr, | |||
815 | * @brief lsfm_fill_static_lsb_hdr_info | 812 | * @brief lsfm_fill_static_lsb_hdr_info |
816 | * Populate static LSB header infomation using the provided ucode image | 813 | * Populate static LSB header infomation using the provided ucode image |
817 | */ | 814 | */ |
818 | static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, | 815 | void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, |
819 | u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode) | 816 | u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode) |
820 | { | 817 | { |
821 | 818 | ||
@@ -886,7 +883,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, | |||
886 | } | 883 | } |
887 | 884 | ||
888 | /* Adds a ucode image to the list of managed ucode images managed. */ | 885 | /* Adds a ucode image to the list of managed ucode images managed. */ |
889 | static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, | 886 | int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, |
890 | struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id) | 887 | struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id) |
891 | { | 888 | { |
892 | struct lsfm_managed_ucode_img_v2 *pnode; | 889 | struct lsfm_managed_ucode_img_v2 *pnode; |
@@ -900,7 +897,7 @@ static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, | |||
900 | 897 | ||
901 | /* Fill in static WPR header info*/ | 898 | /* Fill in static WPR header info*/ |
902 | pnode->wpr_header.falcon_id = falcon_id; | 899 | pnode->wpr_header.falcon_id = falcon_id; |
903 | pnode->wpr_header.bootstrap_owner = 0x07; //LSF_BOOTSTRAP_OWNER_DEFAULT; | 900 | pnode->wpr_header.bootstrap_owner = g->bootstrap_owner; |
904 | pnode->wpr_header.status = LSF_IMAGE_STATUS_COPY; | 901 | pnode->wpr_header.status = LSF_IMAGE_STATUS_COPY; |
905 | 902 | ||
906 | pnode->wpr_header.lazy_bootstrap = | 903 | pnode->wpr_header.lazy_bootstrap = |
@@ -917,7 +914,7 @@ static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, | |||
917 | } | 914 | } |
918 | 915 | ||
919 | /* Free any ucode image structure resources. */ | 916 | /* Free any ucode image structure resources. */ |
920 | static void lsfm_free_ucode_img_res(struct gk20a *g, | 917 | void lsfm_free_ucode_img_res(struct gk20a *g, |
921 | struct flcn_ucode_img_v1 *p_img) | 918 | struct flcn_ucode_img_v1 *p_img) |
922 | { | 919 | { |
923 | if (p_img->lsf_desc != NULL) { | 920 | if (p_img->lsf_desc != NULL) { |
@@ -927,7 +924,7 @@ static void lsfm_free_ucode_img_res(struct gk20a *g, | |||
927 | } | 924 | } |
928 | 925 | ||
929 | /* Free any ucode image structure resources. */ | 926 | /* Free any ucode image structure resources. */ |
930 | static void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g, | 927 | void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g, |
931 | struct flcn_ucode_img_v1 *p_img) | 928 | struct flcn_ucode_img_v1 *p_img) |
932 | { | 929 | { |
933 | if (p_img->lsf_desc != NULL) { | 930 | if (p_img->lsf_desc != NULL) { |
@@ -940,7 +937,7 @@ static void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g, | |||
940 | } | 937 | } |
941 | } | 938 | } |
942 | 939 | ||
943 | static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm) | 940 | void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm) |
944 | { | 941 | { |
945 | u32 cnt = plsfm->managed_flcn_cnt; | 942 | u32 cnt = plsfm->managed_flcn_cnt; |
946 | struct lsfm_managed_ucode_img_v2 *mg_ucode_img; | 943 | struct lsfm_managed_ucode_img_v2 *mg_ucode_img; |
@@ -960,7 +957,7 @@ static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm) | |||
960 | } | 957 | } |
961 | 958 | ||
962 | /* Generate WPR requirements for ACR allocation request */ | 959 | /* Generate WPR requirements for ACR allocation request */ |
963 | static int lsf_gen_wpr_requirements(struct gk20a *g, | 960 | int lsf_gen_wpr_requirements(struct gk20a *g, |
964 | struct ls_flcn_mgr_v1 *plsfm) | 961 | struct ls_flcn_mgr_v1 *plsfm) |
965 | { | 962 | { |
966 | struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list; | 963 | struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list; |
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.h b/drivers/gpu/nvgpu/gp106/acr_gp106.h index 34d2b117..fe8fbdb1 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.h | |||
@@ -20,5 +20,31 @@ | |||
20 | #define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin" | 20 | #define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin" |
21 | 21 | ||
22 | void gp106_init_secure_pmu(struct gpu_ops *gops); | 22 | void gp106_init_secure_pmu(struct gpu_ops *gops); |
23 | void lsfm_free_ucode_img_res(struct gk20a *g, | ||
24 | struct flcn_ucode_img_v1 *p_img); | ||
25 | void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g, | ||
26 | struct flcn_ucode_img_v1 *p_img); | ||
27 | int lsf_gen_wpr_requirements(struct gk20a *g, | ||
28 | struct ls_flcn_mgr_v1 *plsfm); | ||
29 | void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm); | ||
30 | void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, | ||
31 | u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode); | ||
32 | int gp106_pmu_populate_loader_cfg(struct gk20a *g, | ||
33 | void *lsfm, u32 *p_bl_gen_desc_size); | ||
23 | 34 | ||
35 | int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img); | ||
36 | int fecs_ucode_details(struct gk20a *g, | ||
37 | struct flcn_ucode_img_v1 *p_img); | ||
38 | int gpccs_ucode_details(struct gk20a *g, | ||
39 | struct flcn_ucode_img_v1 *p_img); | ||
40 | int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, | ||
41 | struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id); | ||
42 | int lsfm_discover_ucode_images(struct gk20a *g, | ||
43 | struct ls_flcn_mgr_v1 *plsfm); | ||
44 | void lsfm_init_wpr_contents(struct gk20a *g, | ||
45 | struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *nonwpr); | ||
46 | int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g, | ||
47 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); | ||
48 | int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | ||
49 | struct lsfm_managed_ucode_img_v2 *pnode); | ||
24 | #endif /*__PMU_GP106_H_*/ | 50 | #endif /*__PMU_GP106_H_*/ |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 14f7dc2e..2ebf93e2 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -326,6 +326,7 @@ int gp106_init_hal(struct gk20a *g) | |||
326 | gops->privsecurity = 1; | 326 | gops->privsecurity = 1; |
327 | gops->securegpccs = 1; | 327 | gops->securegpccs = 1; |
328 | gops->pmupstate = true; | 328 | gops->pmupstate = true; |
329 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | ||
329 | gk20a_init_bus(gops); | 330 | gk20a_init_bus(gops); |
330 | gp10b_init_priv_ring(gops); | 331 | gp10b_init_priv_ring(gops); |
331 | gp106_init_gr(gops); | 332 | gp106_init_gr(gops); |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 627280ae..796d26dd 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -308,7 +308,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
308 | } | 308 | } |
309 | } | 309 | } |
310 | #endif | 310 | #endif |
311 | 311 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | |
312 | gk20a_init_bus(gops); | 312 | gk20a_init_bus(gops); |
313 | gp10b_init_priv_ring(gops); | 313 | gp10b_init_priv_ring(gops); |
314 | gp10b_init_gr(gops); | 314 | gp10b_init_gr(gops); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h index 89edcefa..ff13be83 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | |||
@@ -26,6 +26,7 @@ | |||
26 | #define LSF_FALCON_ID_RESERVED (1) | 26 | #define LSF_FALCON_ID_RESERVED (1) |
27 | #define LSF_FALCON_ID_FECS (2) | 27 | #define LSF_FALCON_ID_FECS (2) |
28 | #define LSF_FALCON_ID_GPCCS (3) | 28 | #define LSF_FALCON_ID_GPCCS (3) |
29 | #define LSF_FALCON_ID_SEC2 (7) | ||
29 | #define LSF_FALCON_ID_END (11) | 30 | #define LSF_FALCON_ID_END (11) |
30 | #define LSF_FALCON_ID_INVALID (0xFFFFFFFF) | 31 | #define LSF_FALCON_ID_INVALID (0xFFFFFFFF) |
31 | 32 | ||