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authorAlex Frid <afrid@nvidia.com>2017-06-30 16:28:01 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-30 22:35:47 -0400
commit4ed0bfbd806e6fa95b14dfb5162f08d458842130 (patch)
treea70d7f12c5bca2282b0560609c8ca3d12034bc2b /drivers/gpu/nvgpu
parenta34d44b3487b6933e5abf305cccbbd4f15cec05b (diff)
gpu: nvgpu: Init cfg variable to avoid warning
Change-Id: I485e4267766b5e906d1ea5e19ff33712fb4ff8df Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: https://git-master/r/1511785 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Samuel Payne <spayne@nvidia.com> Tested-by: Samuel Payne <spayne@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/gm20b/clk_gm20b.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index b0e72552..e28a31c8 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -454,7 +454,7 @@ static void clk_setup_dvfs_detection(struct gk20a *g, struct pll *gpll)
454/* Enable NA/DVFS mode */ 454/* Enable NA/DVFS mode */
455static int clk_enbale_pll_dvfs(struct gk20a *g) 455static int clk_enbale_pll_dvfs(struct gk20a *g)
456{ 456{
457 u32 data, cfg; 457 u32 data, cfg = 0;
458 int delay = gpc_pll_params.iddq_exit_delay; /* iddq & calib delay */ 458 int delay = gpc_pll_params.iddq_exit_delay; /* iddq & calib delay */
459 struct pll_parms *p = &gpc_pll_params; 459 struct pll_parms *p = &gpc_pll_params;
460 bool calibrated = p->uvdet_slope && p->uvdet_offs; 460 bool calibrated = p->uvdet_slope && p->uvdet_offs;