diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-08-13 17:55:04 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-22 20:32:12 -0400 |
commit | 447a7697e6da888b1559781148fb2a8076ab4e45 (patch) | |
tree | 092c23d4790526ee4ed92d6ed51e7392aaff6454 /drivers/gpu/nvgpu | |
parent | 07f6739285140d7c5335ddcb8996450966bfc175 (diff) |
gpu: nvgpu: Scrub gp10b vgpu HALs
vgpu does not have access to registers. Go through vgpu gp10b HAL and
find all functions that would access a register. Replace each of them
with a NULL.
Change-Id: I32e91c85f128958ba03d2b8303fa9ff11615498f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1798507
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 350 |
1 files changed, 161 insertions, 189 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 00efe316..070339d2 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -81,15 +81,15 @@ | |||
81 | static const struct gpu_ops vgpu_gp10b_ops = { | 81 | static const struct gpu_ops vgpu_gp10b_ops = { |
82 | .ltc = { | 82 | .ltc = { |
83 | .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, | 83 | .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, |
84 | .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, | 84 | .set_zbc_color_entry = NULL, |
85 | .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, | 85 | .set_zbc_depth_entry = NULL, |
86 | .init_cbc = gm20b_ltc_init_cbc, | 86 | .init_cbc = NULL, |
87 | .init_fs_state = vgpu_ltc_init_fs_state, | 87 | .init_fs_state = vgpu_ltc_init_fs_state, |
88 | .init_comptags = vgpu_ltc_init_comptags, | 88 | .init_comptags = vgpu_ltc_init_comptags, |
89 | .cbc_ctrl = NULL, | 89 | .cbc_ctrl = NULL, |
90 | .isr = gp10b_ltc_isr, | 90 | .isr = NULL, |
91 | .cbc_fix_config = gm20b_ltc_cbc_fix_config, | 91 | .cbc_fix_config = NULL, |
92 | .flush = gm20b_flush_ltc, | 92 | .flush = NULL, |
93 | .set_enabled = NULL, | 93 | .set_enabled = NULL, |
94 | .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr, | 94 | .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr, |
95 | .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr, | 95 | .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr, |
@@ -98,13 +98,13 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
98 | .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr, | 98 | .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr, |
99 | }, | 99 | }, |
100 | .ce2 = { | 100 | .ce2 = { |
101 | .isr_stall = gp10b_ce_isr, | 101 | .isr_stall = NULL, |
102 | .isr_nonstall = gp10b_ce_nonstall_isr, | 102 | .isr_nonstall = NULL, |
103 | .get_num_pce = vgpu_ce_get_num_pce, | 103 | .get_num_pce = vgpu_ce_get_num_pce, |
104 | }, | 104 | }, |
105 | .gr = { | 105 | .gr = { |
106 | .get_patch_slots = gr_gk20a_get_patch_slots, | 106 | .get_patch_slots = gr_gk20a_get_patch_slots, |
107 | .init_gpc_mmu = gr_gm20b_init_gpc_mmu, | 107 | .init_gpc_mmu = NULL, |
108 | .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, | 108 | .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, |
109 | .cb_size_default = gr_gp10b_cb_size_default, | 109 | .cb_size_default = gr_gp10b_cb_size_default, |
110 | .calc_global_ctx_buffer_size = | 110 | .calc_global_ctx_buffer_size = |
@@ -113,21 +113,20 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
113 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | 113 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, |
114 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | 114 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, |
115 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | 115 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, |
116 | .handle_sw_method = gr_gp10b_handle_sw_method, | 116 | .handle_sw_method = NULL, |
117 | .set_alpha_circular_buffer_size = | 117 | .set_alpha_circular_buffer_size = NULL, |
118 | gr_gp10b_set_alpha_circular_buffer_size, | 118 | .set_circular_buffer_size = NULL, |
119 | .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size, | 119 | .enable_hww_exceptions = NULL, |
120 | .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions, | ||
121 | .is_valid_class = gr_gp10b_is_valid_class, | 120 | .is_valid_class = gr_gp10b_is_valid_class, |
122 | .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, | 121 | .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, |
123 | .is_valid_compute_class = gr_gp10b_is_valid_compute_class, | 122 | .is_valid_compute_class = gr_gp10b_is_valid_compute_class, |
124 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, | 123 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, |
125 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, | 124 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, |
126 | .init_fs_state = vgpu_gr_init_fs_state, | 125 | .init_fs_state = vgpu_gr_init_fs_state, |
127 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, | 126 | .set_hww_esr_report_mask = NULL, |
128 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | 127 | .falcon_load_ucode = NULL, |
129 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | 128 | .load_ctxsw_ucode = NULL, |
130 | .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, | 129 | .set_gpc_tpc_mask = NULL, |
131 | .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, | 130 | .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, |
132 | .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, | 131 | .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, |
133 | .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, | 132 | .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, |
@@ -135,12 +134,12 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
135 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | 134 | .is_tpc_addr = gr_gm20b_is_tpc_addr, |
136 | .get_tpc_num = gr_gm20b_get_tpc_num, | 135 | .get_tpc_num = gr_gm20b_get_tpc_num, |
137 | .detect_sm_arch = vgpu_gr_detect_sm_arch, | 136 | .detect_sm_arch = vgpu_gr_detect_sm_arch, |
138 | .add_zbc_color = gr_gp10b_add_zbc_color, | 137 | .add_zbc_color = NULL, |
139 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | 138 | .add_zbc_depth = NULL, |
140 | .zbc_set_table = vgpu_gr_add_zbc, | 139 | .zbc_set_table = vgpu_gr_add_zbc, |
141 | .zbc_query_table = vgpu_gr_query_zbc, | 140 | .zbc_query_table = vgpu_gr_query_zbc, |
142 | .pmu_save_zbc = gk20a_pmu_save_zbc, | 141 | .pmu_save_zbc = NULL, |
143 | .add_zbc = gr_gk20a_add_zbc, | 142 | .add_zbc = NULL, |
144 | .pagepool_default_size = gr_gp10b_pagepool_default_size, | 143 | .pagepool_default_size = gr_gp10b_pagepool_default_size, |
145 | .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, | 144 | .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, |
146 | .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, | 145 | .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, |
@@ -155,67 +154,67 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
155 | .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, | 154 | .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, |
156 | .get_max_fbps_count = vgpu_gr_get_max_fbps_count, | 155 | .get_max_fbps_count = vgpu_gr_get_max_fbps_count, |
157 | .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, | 156 | .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, |
158 | .wait_empty = gr_gp10b_wait_empty, | 157 | .wait_empty = NULL, |
159 | .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, | 158 | .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, |
160 | .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, | 159 | .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, |
161 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | 160 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, |
162 | .bpt_reg_info = gr_gm20b_bpt_reg_info, | 161 | .bpt_reg_info = NULL, |
163 | .get_access_map = gr_gp10b_get_access_map, | 162 | .get_access_map = gr_gp10b_get_access_map, |
164 | .handle_fecs_error = gr_gp10b_handle_fecs_error, | 163 | .handle_fecs_error = NULL, |
165 | .handle_sm_exception = gr_gp10b_handle_sm_exception, | 164 | .handle_sm_exception = NULL, |
166 | .handle_tex_exception = gr_gp10b_handle_tex_exception, | 165 | .handle_tex_exception = NULL, |
167 | .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions, | 166 | .enable_gpc_exceptions = NULL, |
168 | .enable_exceptions = gk20a_gr_enable_exceptions, | 167 | .enable_exceptions = NULL, |
169 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | 168 | .get_lrf_tex_ltc_dram_override = NULL, |
170 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, | 169 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, |
171 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | 170 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, |
172 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | 171 | .record_sm_error_state = gm20b_gr_record_sm_error_state, |
173 | .update_sm_error_state = gm20b_gr_update_sm_error_state, | 172 | .update_sm_error_state = NULL, |
174 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | 173 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, |
175 | .suspend_contexts = vgpu_gr_suspend_contexts, | 174 | .suspend_contexts = vgpu_gr_suspend_contexts, |
176 | .resume_contexts = vgpu_gr_resume_contexts, | 175 | .resume_contexts = vgpu_gr_resume_contexts, |
177 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | 176 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, |
178 | .init_sm_id_table = vgpu_gr_init_sm_id_table, | 177 | .init_sm_id_table = vgpu_gr_init_sm_id_table, |
179 | .load_smid_config = gr_gp10b_load_smid_config, | 178 | .load_smid_config = NULL, |
180 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, | 179 | .program_sm_id_numbering = NULL, |
181 | .setup_rop_mapping = gr_gk20a_setup_rop_mapping, | 180 | .setup_rop_mapping = NULL, |
182 | .program_zcull_mapping = gr_gk20a_program_zcull_mapping, | 181 | .program_zcull_mapping = NULL, |
183 | .commit_global_timeslice = gr_gk20a_commit_global_timeslice, | 182 | .commit_global_timeslice = NULL, |
184 | .commit_inst = vgpu_gr_commit_inst, | 183 | .commit_inst = vgpu_gr_commit_inst, |
185 | .write_zcull_ptr = gr_gk20a_write_zcull_ptr, | 184 | .write_zcull_ptr = gr_gk20a_write_zcull_ptr, |
186 | .write_pm_ptr = gr_gk20a_write_pm_ptr, | 185 | .write_pm_ptr = gr_gk20a_write_pm_ptr, |
187 | .load_tpc_mask = gr_gm20b_load_tpc_mask, | 186 | .load_tpc_mask = NULL, |
188 | .trigger_suspend = gr_gk20a_trigger_suspend, | 187 | .trigger_suspend = NULL, |
189 | .wait_for_pause = gr_gk20a_wait_for_pause, | 188 | .wait_for_pause = gr_gk20a_wait_for_pause, |
190 | .resume_from_pause = gr_gk20a_resume_from_pause, | 189 | .resume_from_pause = NULL, |
191 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | 190 | .clear_sm_errors = gr_gk20a_clear_sm_errors, |
192 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | 191 | .tpc_enabled_exceptions = NULL, |
193 | .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, | 192 | .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, |
194 | .sm_debugger_attached = gk20a_gr_sm_debugger_attached, | 193 | .sm_debugger_attached = NULL, |
195 | .suspend_single_sm = gk20a_gr_suspend_single_sm, | 194 | .suspend_single_sm = NULL, |
196 | .suspend_all_sms = gk20a_gr_suspend_all_sms, | 195 | .suspend_all_sms = NULL, |
197 | .resume_single_sm = gk20a_gr_resume_single_sm, | 196 | .resume_single_sm = NULL, |
198 | .resume_all_sms = gk20a_gr_resume_all_sms, | 197 | .resume_all_sms = NULL, |
199 | .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr, | 198 | .get_sm_hww_warp_esr = NULL, |
200 | .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr, | 199 | .get_sm_hww_global_esr = NULL, |
201 | .get_sm_no_lock_down_hww_global_esr_mask = | 200 | .get_sm_no_lock_down_hww_global_esr_mask = |
202 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, | 201 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, |
203 | .lock_down_sm = gk20a_gr_lock_down_sm, | 202 | .lock_down_sm = NULL, |
204 | .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, | 203 | .wait_for_sm_lock_down = NULL, |
205 | .clear_sm_hww = gm20b_gr_clear_sm_hww, | 204 | .clear_sm_hww = NULL, |
206 | .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, | 205 | .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, |
207 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, | 206 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, |
208 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | 207 | .disable_rd_coalesce = NULL, |
209 | .set_boosted_ctx = NULL, | 208 | .set_boosted_ctx = NULL, |
210 | .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, | 209 | .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, |
211 | .set_czf_bypass = gr_gp10b_set_czf_bypass, | 210 | .set_czf_bypass = NULL, |
212 | .init_czf_bypass = gr_gp10b_init_czf_bypass, | 211 | .init_czf_bypass = gr_gp10b_init_czf_bypass, |
213 | .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception, | 212 | .pre_process_sm_exception = NULL, |
214 | .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va, | 213 | .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va, |
215 | .init_preemption_state = gr_gp10b_init_preemption_state, | 214 | .init_preemption_state = NULL, |
216 | .update_boosted_ctx = NULL, | 215 | .update_boosted_ctx = NULL, |
217 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | 216 | .set_bes_crop_debug3 = NULL, |
218 | .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, | 217 | .set_bes_crop_debug4 = NULL, |
219 | .set_ctxsw_preemption_mode = | 218 | .set_ctxsw_preemption_mode = |
220 | vgpu_gr_gp10b_set_ctxsw_preemption_mode, | 219 | vgpu_gr_gp10b_set_ctxsw_preemption_mode, |
221 | .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, | 220 | .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, |
@@ -237,71 +236,46 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
237 | gr_gk20a_get_offset_in_gpccs_segment, | 236 | gr_gk20a_get_offset_in_gpccs_segment, |
238 | }, | 237 | }, |
239 | .fb = { | 238 | .fb = { |
240 | .reset = fb_gk20a_reset, | 239 | .reset = NULL, |
241 | .init_hw = gk20a_fb_init_hw, | 240 | .init_hw = NULL, |
242 | .init_fs_state = fb_gm20b_init_fs_state, | 241 | .init_fs_state = NULL, |
243 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | 242 | .set_mmu_page_size = NULL, |
244 | .set_use_full_comp_tag_line = | 243 | .set_use_full_comp_tag_line = NULL, |
245 | gm20b_fb_set_use_full_comp_tag_line, | ||
246 | .compression_page_size = gp10b_fb_compression_page_size, | 244 | .compression_page_size = gp10b_fb_compression_page_size, |
247 | .compressible_page_size = gp10b_fb_compressible_page_size, | 245 | .compressible_page_size = gp10b_fb_compressible_page_size, |
248 | .compression_align_mask = gm20b_fb_compression_align_mask, | 246 | .compression_align_mask = gm20b_fb_compression_align_mask, |
249 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | 247 | .vpr_info_fetch = NULL, |
250 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | 248 | .dump_vpr_wpr_info = NULL, |
251 | .read_wpr_info = gm20b_fb_read_wpr_info, | 249 | .read_wpr_info = NULL, |
252 | .is_debug_mode_enabled = NULL, | 250 | .is_debug_mode_enabled = NULL, |
253 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | 251 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, |
254 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | 252 | .tlb_invalidate = vgpu_mm_tlb_invalidate, |
255 | }, | 253 | }, |
256 | .clock_gating = { | 254 | .clock_gating = { |
257 | .slcg_bus_load_gating_prod = | 255 | .slcg_bus_load_gating_prod = NULL, |
258 | gp10b_slcg_bus_load_gating_prod, | 256 | .slcg_ce2_load_gating_prod = NULL, |
259 | .slcg_ce2_load_gating_prod = | 257 | .slcg_chiplet_load_gating_prod = NULL, |
260 | gp10b_slcg_ce2_load_gating_prod, | 258 | .slcg_ctxsw_firmware_load_gating_prod = NULL, |
261 | .slcg_chiplet_load_gating_prod = | 259 | .slcg_fb_load_gating_prod = NULL, |
262 | gp10b_slcg_chiplet_load_gating_prod, | 260 | .slcg_fifo_load_gating_prod = NULL, |
263 | .slcg_ctxsw_firmware_load_gating_prod = | 261 | .slcg_gr_load_gating_prod = NULL, |
264 | gp10b_slcg_ctxsw_firmware_load_gating_prod, | 262 | .slcg_ltc_load_gating_prod = NULL, |
265 | .slcg_fb_load_gating_prod = | 263 | .slcg_perf_load_gating_prod = NULL, |
266 | gp10b_slcg_fb_load_gating_prod, | 264 | .slcg_priring_load_gating_prod = NULL, |
267 | .slcg_fifo_load_gating_prod = | 265 | .slcg_pmu_load_gating_prod = NULL, |
268 | gp10b_slcg_fifo_load_gating_prod, | 266 | .slcg_therm_load_gating_prod = NULL, |
269 | .slcg_gr_load_gating_prod = | 267 | .slcg_xbar_load_gating_prod = NULL, |
270 | gr_gp10b_slcg_gr_load_gating_prod, | 268 | .blcg_bus_load_gating_prod = NULL, |
271 | .slcg_ltc_load_gating_prod = | 269 | .blcg_ce_load_gating_prod = NULL, |
272 | ltc_gp10b_slcg_ltc_load_gating_prod, | 270 | .blcg_ctxsw_firmware_load_gating_prod = NULL, |
273 | .slcg_perf_load_gating_prod = | 271 | .blcg_fb_load_gating_prod = NULL, |
274 | gp10b_slcg_perf_load_gating_prod, | 272 | .blcg_fifo_load_gating_prod = NULL, |
275 | .slcg_priring_load_gating_prod = | 273 | .blcg_gr_load_gating_prod = NULL, |
276 | gp10b_slcg_priring_load_gating_prod, | 274 | .blcg_ltc_load_gating_prod = NULL, |
277 | .slcg_pmu_load_gating_prod = | 275 | .blcg_pwr_csb_load_gating_prod = NULL, |
278 | gp10b_slcg_pmu_load_gating_prod, | 276 | .blcg_pmu_load_gating_prod = NULL, |
279 | .slcg_therm_load_gating_prod = | 277 | .blcg_xbar_load_gating_prod = NULL, |
280 | gp10b_slcg_therm_load_gating_prod, | 278 | .pg_gr_load_gating_prod = NULL, |
281 | .slcg_xbar_load_gating_prod = | ||
282 | gp10b_slcg_xbar_load_gating_prod, | ||
283 | .blcg_bus_load_gating_prod = | ||
284 | gp10b_blcg_bus_load_gating_prod, | ||
285 | .blcg_ce_load_gating_prod = | ||
286 | gp10b_blcg_ce_load_gating_prod, | ||
287 | .blcg_ctxsw_firmware_load_gating_prod = | ||
288 | gp10b_blcg_ctxsw_firmware_load_gating_prod, | ||
289 | .blcg_fb_load_gating_prod = | ||
290 | gp10b_blcg_fb_load_gating_prod, | ||
291 | .blcg_fifo_load_gating_prod = | ||
292 | gp10b_blcg_fifo_load_gating_prod, | ||
293 | .blcg_gr_load_gating_prod = | ||
294 | gp10b_blcg_gr_load_gating_prod, | ||
295 | .blcg_ltc_load_gating_prod = | ||
296 | gp10b_blcg_ltc_load_gating_prod, | ||
297 | .blcg_pwr_csb_load_gating_prod = | ||
298 | gp10b_blcg_pwr_csb_load_gating_prod, | ||
299 | .blcg_pmu_load_gating_prod = | ||
300 | gp10b_blcg_pmu_load_gating_prod, | ||
301 | .blcg_xbar_load_gating_prod = | ||
302 | gp10b_blcg_xbar_load_gating_prod, | ||
303 | .pg_gr_load_gating_prod = | ||
304 | gr_gp10b_pg_gr_load_gating_prod, | ||
305 | }, | 279 | }, |
306 | .fifo = { | 280 | .fifo = { |
307 | .init_fifo_setup_hw = vgpu_init_fifo_setup_hw, | 281 | .init_fifo_setup_hw = vgpu_init_fifo_setup_hw, |
@@ -326,8 +300,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
326 | .tsg_verify_status_ctx_reload = NULL, | 300 | .tsg_verify_status_ctx_reload = NULL, |
327 | .reschedule_runlist = NULL, | 301 | .reschedule_runlist = NULL, |
328 | .update_runlist = vgpu_fifo_update_runlist, | 302 | .update_runlist = vgpu_fifo_update_runlist, |
329 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | 303 | .trigger_mmu_fault = NULL, |
330 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, | 304 | .get_mmu_fault_info = NULL, |
331 | .get_mmu_fault_desc = gp10b_fifo_get_mmu_fault_desc, | 305 | .get_mmu_fault_desc = gp10b_fifo_get_mmu_fault_desc, |
332 | .get_mmu_fault_client_desc = gp10b_fifo_get_mmu_fault_client_desc, | 306 | .get_mmu_fault_client_desc = gp10b_fifo_get_mmu_fault_client_desc, |
333 | .get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc, | 307 | .get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc, |
@@ -346,16 +320,16 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
346 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | 320 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, |
347 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | 321 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, |
348 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | 322 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, |
349 | .dump_pbdma_status = gk20a_dump_pbdma_status, | 323 | .dump_pbdma_status = NULL, |
350 | .dump_eng_status = gk20a_dump_eng_status, | 324 | .dump_eng_status = NULL, |
351 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | 325 | .dump_channel_status_ramfc = NULL, |
352 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | 326 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, |
353 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | 327 | .is_preempt_pending = NULL, |
354 | .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, | 328 | .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, |
355 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | 329 | .reset_enable_hw = NULL, |
356 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | 330 | .teardown_ch_tsg = NULL, |
357 | .handle_sched_error = gk20a_fifo_handle_sched_error, | 331 | .handle_sched_error = NULL, |
358 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | 332 | .handle_pbdma_intr_0 = NULL, |
359 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | 333 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, |
360 | .tsg_bind_channel = vgpu_tsg_bind_channel, | 334 | .tsg_bind_channel = vgpu_tsg_bind_channel, |
361 | .tsg_unbind_channel = vgpu_tsg_unbind_channel, | 335 | .tsg_unbind_channel = vgpu_tsg_unbind_channel, |
@@ -380,8 +354,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
380 | #endif | 354 | #endif |
381 | .resetup_ramfc = NULL, | 355 | .resetup_ramfc = NULL, |
382 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | 356 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, |
383 | .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, | 357 | .runlist_hw_submit = NULL, |
384 | .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, | 358 | .runlist_wait_pending = NULL, |
385 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 359 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, |
386 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 360 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, |
387 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 361 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, |
@@ -418,7 +392,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
418 | .fb_flush = vgpu_mm_fb_flush, | 392 | .fb_flush = vgpu_mm_fb_flush, |
419 | .l2_invalidate = vgpu_mm_l2_invalidate, | 393 | .l2_invalidate = vgpu_mm_l2_invalidate, |
420 | .l2_flush = vgpu_mm_l2_flush, | 394 | .l2_flush = vgpu_mm_l2_flush, |
421 | .cbc_clean = gk20a_mm_cbc_clean, | 395 | .cbc_clean = NULL, |
422 | .set_big_page_size = gm20b_mm_set_big_page_size, | 396 | .set_big_page_size = gm20b_mm_set_big_page_size, |
423 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | 397 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, |
424 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | 398 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, |
@@ -429,44 +403,44 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
429 | .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, | 403 | .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, |
430 | .is_bar1_supported = gm20b_mm_is_bar1_supported, | 404 | .is_bar1_supported = gm20b_mm_is_bar1_supported, |
431 | .init_inst_block = gk20a_init_inst_block, | 405 | .init_inst_block = gk20a_init_inst_block, |
432 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | 406 | .mmu_fault_pending = NULL, |
433 | .init_bar2_vm = gp10b_init_bar2_vm, | 407 | .init_bar2_vm = gp10b_init_bar2_vm, |
434 | .remove_bar2_vm = gp10b_remove_bar2_vm, | 408 | .remove_bar2_vm = gp10b_remove_bar2_vm, |
435 | .get_kind_invalid = gm20b_get_kind_invalid, | 409 | .get_kind_invalid = gm20b_get_kind_invalid, |
436 | .get_kind_pitch = gm20b_get_kind_pitch, | 410 | .get_kind_pitch = gm20b_get_kind_pitch, |
437 | }, | 411 | }, |
438 | .pramin = { | 412 | .pramin = { |
439 | .data032_r = pram_data032_r, | 413 | .data032_r = NULL, |
440 | }, | 414 | }, |
441 | .therm = { | 415 | .therm = { |
442 | .init_therm_setup_hw = gp10b_init_therm_setup_hw, | 416 | .init_therm_setup_hw = NULL, |
443 | .init_elcg_mode = gm20b_therm_init_elcg_mode, | 417 | .init_elcg_mode = NULL, |
444 | .init_blcg_mode = gm20b_therm_init_blcg_mode, | 418 | .init_blcg_mode = NULL, |
445 | .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, | 419 | .elcg_init_idle_filters = NULL, |
446 | }, | 420 | }, |
447 | .pmu = { | 421 | .pmu = { |
448 | .pmu_setup_elpg = gp10b_pmu_setup_elpg, | 422 | .pmu_setup_elpg = NULL, |
449 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | 423 | .pmu_get_queue_head = NULL, |
450 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | 424 | .pmu_get_queue_head_size = NULL, |
451 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | 425 | .pmu_get_queue_tail = NULL, |
452 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | 426 | .pmu_get_queue_tail_size = NULL, |
453 | .pmu_queue_head = gk20a_pmu_queue_head, | 427 | .pmu_queue_head = NULL, |
454 | .pmu_queue_tail = gk20a_pmu_queue_tail, | 428 | .pmu_queue_tail = NULL, |
455 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | 429 | .pmu_msgq_tail = NULL, |
456 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | 430 | .pmu_mutex_size = NULL, |
457 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | 431 | .pmu_mutex_acquire = NULL, |
458 | .pmu_mutex_release = gk20a_pmu_mutex_release, | 432 | .pmu_mutex_release = NULL, |
459 | .write_dmatrfbase = gp10b_write_dmatrfbase, | 433 | .write_dmatrfbase = NULL, |
460 | .pmu_elpg_statistics = gp10b_pmu_elpg_statistics, | 434 | .pmu_elpg_statistics = NULL, |
461 | .pmu_init_perfmon = nvgpu_pmu_init_perfmon, | 435 | .pmu_init_perfmon = NULL, |
462 | .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling, | 436 | .pmu_perfmon_start_sampling = NULL, |
463 | .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling, | 437 | .pmu_perfmon_stop_sampling = NULL, |
464 | .pmu_pg_init_param = gp10b_pg_gr_init, | 438 | .pmu_pg_init_param = NULL, |
465 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | 439 | .pmu_pg_supported_engines_list = NULL, |
466 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | 440 | .pmu_pg_engines_feature_list = NULL, |
467 | .dump_secure_fuses = pmu_dump_security_fuses_gm20b, | 441 | .dump_secure_fuses = NULL, |
468 | .reset_engine = gk20a_pmu_engine_reset, | 442 | .reset_engine = NULL, |
469 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, | 443 | .is_engine_in_reset = NULL, |
470 | }, | 444 | }, |
471 | .regops = { | 445 | .regops = { |
472 | .exec_regops = vgpu_exec_regops, | 446 | .exec_regops = vgpu_exec_regops, |
@@ -493,23 +467,23 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
493 | .apply_smpc_war = gp10b_apply_smpc_war, | 467 | .apply_smpc_war = gp10b_apply_smpc_war, |
494 | }, | 468 | }, |
495 | .mc = { | 469 | .mc = { |
496 | .intr_mask = mc_gp10b_intr_mask, | 470 | .intr_mask = NULL, |
497 | .intr_enable = mc_gp10b_intr_enable, | 471 | .intr_enable = NULL, |
498 | .intr_unit_config = mc_gp10b_intr_unit_config, | 472 | .intr_unit_config = NULL, |
499 | .isr_stall = mc_gp10b_isr_stall, | 473 | .isr_stall = NULL, |
500 | .intr_stall = mc_gp10b_intr_stall, | 474 | .intr_stall = NULL, |
501 | .intr_stall_pause = mc_gp10b_intr_stall_pause, | 475 | .intr_stall_pause = NULL, |
502 | .intr_stall_resume = mc_gp10b_intr_stall_resume, | 476 | .intr_stall_resume = NULL, |
503 | .intr_nonstall = mc_gp10b_intr_nonstall, | 477 | .intr_nonstall = NULL, |
504 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | 478 | .intr_nonstall_pause = NULL, |
505 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | 479 | .intr_nonstall_resume = NULL, |
506 | .isr_nonstall = mc_gk20a_isr_nonstall, | 480 | .isr_nonstall = NULL, |
507 | .enable = gk20a_mc_enable, | 481 | .enable = NULL, |
508 | .disable = gk20a_mc_disable, | 482 | .disable = NULL, |
509 | .reset = gk20a_mc_reset, | 483 | .reset = NULL, |
510 | .boot_0 = gk20a_mc_boot_0, | 484 | .boot_0 = NULL, |
511 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | 485 | .is_intr1_pending = NULL, |
512 | .log_pending_intrs = mc_gp10b_log_pending_intrs, | 486 | .log_pending_intrs = NULL, |
513 | }, | 487 | }, |
514 | .debug = { | 488 | .debug = { |
515 | .show_dump = NULL, | 489 | .show_dump = NULL, |
@@ -529,11 +503,11 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
529 | .perfbuffer_disable = vgpu_perfbuffer_disable, | 503 | .perfbuffer_disable = vgpu_perfbuffer_disable, |
530 | }, | 504 | }, |
531 | .bus = { | 505 | .bus = { |
532 | .init_hw = gk20a_bus_init_hw, | 506 | .init_hw = NULL, |
533 | .isr = gk20a_bus_isr, | 507 | .isr = NULL, |
534 | .bar1_bind = NULL, | 508 | .bar1_bind = NULL, |
535 | .bar2_bind = NULL, | 509 | .bar2_bind = NULL, |
536 | .set_bar0_window = gk20a_bus_set_bar0_window, | 510 | .set_bar0_window = NULL, |
537 | }, | 511 | }, |
538 | .ptimer = { | 512 | .ptimer = { |
539 | .isr = NULL, | 513 | .isr = NULL, |
@@ -555,24 +529,22 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
555 | .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, | 529 | .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, |
556 | }, | 530 | }, |
557 | .priv_ring = { | 531 | .priv_ring = { |
558 | .enable_priv_ring = gm20b_priv_ring_enable, | 532 | .enable_priv_ring = NULL, |
559 | .isr = gp10b_priv_ring_isr, | 533 | .isr = NULL, |
560 | .set_ppriv_timeout_settings = | 534 | .set_ppriv_timeout_settings = NULL, |
561 | gm20b_priv_set_timeout_settings, | 535 | .enum_ltc = NULL, |
562 | .enum_ltc = gm20b_priv_ring_enum_ltc, | ||
563 | }, | 536 | }, |
564 | .fuse = { | 537 | .fuse = { |
565 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, | 538 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, |
566 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | 539 | .is_opt_ecc_enable = NULL, |
567 | .is_opt_feature_override_disable = | 540 | .is_opt_feature_override_disable = NULL, |
568 | gp10b_fuse_is_opt_feature_override_disable, | 541 | .fuse_status_opt_fbio = NULL, |
569 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | 542 | .fuse_status_opt_fbp = NULL, |
570 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | 543 | .fuse_status_opt_rop_l2_fbp = NULL, |
571 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | 544 | .fuse_status_opt_tpc_gpc = NULL, |
572 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | 545 | .fuse_ctrl_opt_tpc_gpc = NULL, |
573 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | 546 | .fuse_opt_sec_debug_en = NULL, |
574 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | 547 | .fuse_opt_priv_sec_en = NULL, |
575 | .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, | ||
576 | .read_vin_cal_fuse_rev = NULL, | 548 | .read_vin_cal_fuse_rev = NULL, |
577 | .read_vin_cal_slope_intercept_fuse = NULL, | 549 | .read_vin_cal_slope_intercept_fuse = NULL, |
578 | .read_vin_cal_gain_offset_fuse = NULL, | 550 | .read_vin_cal_gain_offset_fuse = NULL, |