diff options
author | Supriya <ssharatkumar@nvidia.com> | 2015-02-09 06:32:00 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 21:06:39 -0400 |
commit | 3d9a83eb5a59f12412b2f08ba88a32244fd195ca (patch) | |
tree | 048433e67db8475ba275e23d8c5257abfcc9e352 /drivers/gpu/nvgpu | |
parent | 50d5ed2eefd6c74bc8e5625c83763c7c92220dff (diff) |
gpu: nvgpu: gk20a: FECS HALT method
FECS halt method is used to do graceful FECS shutdown.
Bug 1551865
Change-Id: Iec8590e86cb09f9b54c36f85859208fc8650f6a6
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/682459
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 8 |
5 files changed, 37 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 18928142..2740129f 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics FIFO (gr host) | 2 | * GK20A Graphics FIFO (gr host) |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -832,6 +832,9 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
832 | gk20a_dbg_fn(""); | 832 | gk20a_dbg_fn(""); |
833 | 833 | ||
834 | if (engine_id == top_device_info_type_enum_graphics_v()) { | 834 | if (engine_id == top_device_info_type_enum_graphics_v()) { |
835 | /*HALT_PIPELINE method, halt GR engine*/ | ||
836 | if (gr_gk20a_halt_pipe(g)) | ||
837 | gk20a_err(dev_from_gk20a(g), "failed to HALT gr pipe"); | ||
835 | /* resetting engine using mc_enable_r() is not enough, | 838 | /* resetting engine using mc_enable_r() is not enough, |
836 | * we do full init sequence */ | 839 | * we do full init sequence */ |
837 | gk20a_gr_reset(g); | 840 | gk20a_gr_reset(g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 75775d57..8869f4c4 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -536,6 +536,21 @@ int gr_gk20a_enable_ctxsw(struct gk20a *g) | |||
536 | gr_fecs_method_push_adr_start_ctxsw_v(), NULL); | 536 | gr_fecs_method_push_adr_start_ctxsw_v(), NULL); |
537 | } | 537 | } |
538 | 538 | ||
539 | int gr_gk20a_halt_pipe(struct gk20a *g) | ||
540 | { | ||
541 | return gr_gk20a_submit_fecs_method_op(g, | ||
542 | (struct fecs_method_op_gk20a) { | ||
543 | .method.addr = | ||
544 | gr_fecs_method_push_adr_halt_pipeline_v(), | ||
545 | .method.data = ~0, | ||
546 | .mailbox = { .id = 1, /*sideband?*/ | ||
547 | .data = ~0, .clr = ~0, .ret = 0, | ||
548 | .ok = gr_fecs_ctxsw_mailbox_value_pass_v(), | ||
549 | .fail = gr_fecs_ctxsw_mailbox_value_fail_v(), }, | ||
550 | .cond.ok = GR_IS_UCODE_OP_EQUAL, | ||
551 | .cond.fail = GR_IS_UCODE_OP_EQUAL }); | ||
552 | } | ||
553 | |||
539 | 554 | ||
540 | static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va) | 555 | static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va) |
541 | { | 556 | { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 903b2754..0d511499 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics Engine | 2 | * GK20A Graphics Engine |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -497,4 +497,5 @@ int gr_gk20a_alloc_gr_ctx(struct gk20a *g, | |||
497 | u32 class, u32 padding); | 497 | u32 class, u32 padding); |
498 | void gr_gk20a_free_gr_ctx(struct gk20a *g, | 498 | void gr_gk20a_free_gr_ctx(struct gk20a *g, |
499 | struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx); | 499 | struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx); |
500 | int gr_gk20a_halt_pipe(struct gk20a *g); | ||
500 | #endif /*__GR_GK20A_H__*/ | 501 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index 38ffd524..7bd4ab79 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -718,6 +718,10 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) | |||
718 | { | 718 | { |
719 | return 0x21; | 719 | return 0x21; |
720 | } | 720 | } |
721 | static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) | ||
722 | { | ||
723 | return 0x00000004; | ||
724 | } | ||
721 | static inline u32 gr_fecs_host_int_status_r(void) | 725 | static inline u32 gr_fecs_host_int_status_r(void) |
722 | { | 726 | { |
723 | return 0x00409c18; | 727 | return 0x00409c18; |
@@ -1302,10 +1306,6 @@ static inline u32 gr_ds_zbc_color_r_val_f(u32 v) | |||
1302 | { | 1306 | { |
1303 | return (v & 0xffffffff) << 0; | 1307 | return (v & 0xffffffff) << 0; |
1304 | } | 1308 | } |
1305 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
1306 | { | ||
1307 | return 0x00000028; | ||
1308 | } | ||
1309 | static inline u32 gr_ds_zbc_color_g_r(void) | 1309 | static inline u32 gr_ds_zbc_color_g_r(void) |
1310 | { | 1310 | { |
1311 | return 0x00405808; | 1311 | return 0x00405808; |
@@ -1354,6 +1354,10 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) | |||
1354 | { | 1354 | { |
1355 | return 0x00000004; | 1355 | return 0x00000004; |
1356 | } | 1356 | } |
1357 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
1358 | { | ||
1359 | return 0x00000028; | ||
1360 | } | ||
1357 | static inline u32 gr_ds_zbc_z_r(void) | 1361 | static inline u32 gr_ds_zbc_z_r(void) |
1358 | { | 1362 | { |
1359 | return 0x00405818; | 1363 | return 0x00405818; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 714ceb16..23b5226a 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -718,6 +718,10 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) | |||
718 | { | 718 | { |
719 | return 0x21; | 719 | return 0x21; |
720 | } | 720 | } |
721 | static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) | ||
722 | { | ||
723 | return 0x00000004; | ||
724 | } | ||
721 | static inline u32 gr_fecs_host_int_status_r(void) | 725 | static inline u32 gr_fecs_host_int_status_r(void) |
722 | { | 726 | { |
723 | return 0x00409c18; | 727 | return 0x00409c18; |
@@ -1302,6 +1306,10 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) | |||
1302 | { | 1306 | { |
1303 | return 0x00000004; | 1307 | return 0x00000004; |
1304 | } | 1308 | } |
1309 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
1310 | { | ||
1311 | return 0x00000028; | ||
1312 | } | ||
1305 | static inline u32 gr_ds_zbc_z_r(void) | 1313 | static inline u32 gr_ds_zbc_z_r(void) |
1306 | { | 1314 | { |
1307 | return 0x00405818; | 1315 | return 0x00405818; |