diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2017-05-17 23:03:22 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-07 16:35:28 -0400 |
commit | 3bf38954c2cd794485ed1bac50df8e61ad1100eb (patch) | |
tree | db7b2b7e181a72974c2e2e62d69b1bdd11c15aa9 /drivers/gpu/nvgpu | |
parent | 3e22195974ef233e12f69c5769d42b322f5adc1e (diff) |
gpu: nvgpu: gv11b: move cbc init to mmu from ltc
Added cbc_init in fb and removed cbc_init from ltc.
Also avoid writing into read only registers in ltc.
GPUT19X-70
GPUT19X-116
Change-Id: Ife53e8ec7f049d666baacea3b7c45179e3e13ff9
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1484525
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 68 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 80 |
3 files changed, 149 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 9a4ea36b..3b3d775e 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> | 28 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> |
29 | 29 | ||
30 | #include <nvgpu/log.h> | 30 | #include <nvgpu/log.h> |
31 | #include <nvgpu/enabled.h> | ||
31 | 32 | ||
32 | static void gv11b_init_nvlink_soc_credits(struct gk20a *g) | 33 | static void gv11b_init_nvlink_soc_credits(struct gk20a *g) |
33 | { | 34 | { |
@@ -62,6 +63,71 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) | |||
62 | 63 | ||
63 | } | 64 | } |
64 | 65 | ||
66 | static void gv11b_fb_init_fs_state(struct gk20a *g) | ||
67 | { | ||
68 | nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb"); | ||
69 | |||
70 | nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %u", | ||
71 | gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); | ||
72 | |||
73 | gk20a_writel(g, fb_mmu_num_active_ltcs_r(), | ||
74 | fb_mmu_num_active_ltcs_count_f(g->ltc_count)); | ||
75 | |||
76 | nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u", | ||
77 | fb_mmu_num_active_ltcs_count_v( | ||
78 | gk20a_readl(g, fb_mmu_num_active_ltcs_r()))); | ||
79 | } | ||
80 | |||
81 | static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | ||
82 | { | ||
83 | u32 max_size = gr->max_comptag_mem; | ||
84 | /* one tag line covers 64KB */ | ||
85 | u32 max_comptag_lines = max_size << 4; | ||
86 | u32 compbit_base_post_divide; | ||
87 | u64 compbit_base_post_multiply64; | ||
88 | u64 compbit_store_iova; | ||
89 | u64 compbit_base_post_divide64; | ||
90 | |||
91 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) | ||
92 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); | ||
93 | else | ||
94 | compbit_store_iova = g->ops.mm.get_iova_addr(g, | ||
95 | gr->compbit_store.mem.priv.sgt->sgl, 0); | ||
96 | |||
97 | compbit_base_post_divide64 = compbit_store_iova >> | ||
98 | fb_mmu_cbc_base_address_alignment_shift_v(); | ||
99 | |||
100 | do_div(compbit_base_post_divide64, g->ltc_count); | ||
101 | compbit_base_post_divide = u64_lo32(compbit_base_post_divide64); | ||
102 | |||
103 | compbit_base_post_multiply64 = ((u64)compbit_base_post_divide * | ||
104 | g->ltc_count) << fb_mmu_cbc_base_address_alignment_shift_v(); | ||
105 | |||
106 | if (compbit_base_post_multiply64 < compbit_store_iova) | ||
107 | compbit_base_post_divide++; | ||
108 | |||
109 | if (g->ops.ltc.cbc_fix_config) | ||
110 | compbit_base_post_divide = | ||
111 | g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide); | ||
112 | |||
113 | gk20a_writel(g, fb_mmu_cbc_base_r(), | ||
114 | fb_mmu_cbc_base_address_f(compbit_base_post_divide)); | ||
115 | |||
116 | nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte, | ||
117 | "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n", | ||
118 | (u32)(compbit_store_iova >> 32), | ||
119 | (u32)(compbit_store_iova & 0xffffffff), | ||
120 | compbit_base_post_divide); | ||
121 | nvgpu_log(g, gpu_dbg_fn, "cbc base %x", | ||
122 | gk20a_readl(g, fb_mmu_cbc_base_r())); | ||
123 | |||
124 | gr->compbit_store.base_hw = compbit_base_post_divide; | ||
125 | |||
126 | g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate, | ||
127 | 0, max_comptag_lines - 1); | ||
128 | |||
129 | } | ||
130 | |||
65 | static void gv11b_fb_reset(struct gk20a *g) | 131 | static void gv11b_fb_reset(struct gk20a *g) |
66 | { | 132 | { |
67 | u32 val; | 133 | u32 val; |
@@ -450,6 +516,8 @@ void gv11b_init_fb(struct gpu_ops *gops) | |||
450 | gp10b_init_fb(gops); | 516 | gp10b_init_fb(gops); |
451 | gops->fb.hub_isr = gv11b_fb_hub_isr; | 517 | gops->fb.hub_isr = gv11b_fb_hub_isr; |
452 | gops->fb.reset = gv11b_fb_reset; | 518 | gops->fb.reset = gv11b_fb_reset; |
519 | gops->fb.init_fs_state = gv11b_fb_init_fs_state; | ||
520 | gops->fb.init_cbc = gv11b_fb_init_cbc; | ||
453 | 521 | ||
454 | gv11b_init_uncompressed_kind_map(); | 522 | gv11b_init_uncompressed_kind_map(); |
455 | gv11b_init_kind_attr(); | 523 | gv11b_init_kind_attr(); |
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index b8a97ce3..5b98b0aa 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | |||
@@ -53,10 +53,6 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) | |||
53 | g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); | 53 | g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); |
54 | gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); | 54 | gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); |
55 | 55 | ||
56 | reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); | ||
57 | reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); | ||
58 | gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg); | ||
59 | |||
60 | gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), | 56 | gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), |
61 | gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) | | 57 | gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) | |
62 | ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); | 58 | ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); |
@@ -200,4 +196,5 @@ void gv11b_init_ltc(struct gpu_ops *gops) | |||
200 | gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; | 196 | gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; |
201 | gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; | 197 | gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; |
202 | gops->ltc.isr = gv11b_ltc_isr; | 198 | gops->ltc.isr = gv11b_ltc_isr; |
199 | gops->ltc.init_cbc = NULL; | ||
203 | } | 200 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 0ddccd45..e261ef14 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | |||
@@ -1814,4 +1814,84 @@ static inline u32 fb_mmu_fault_status_valid_clear_f(void) | |||
1814 | { | 1814 | { |
1815 | return 0x80000000; | 1815 | return 0x80000000; |
1816 | } | 1816 | } |
1817 | static inline u32 fb_mmu_num_active_ltcs_r(void) | ||
1818 | { | ||
1819 | return 0x00100ec0; | ||
1820 | } | ||
1821 | static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) | ||
1822 | { | ||
1823 | return (v & 0x1f) << 0; | ||
1824 | } | ||
1825 | static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) | ||
1826 | { | ||
1827 | return (r >> 0) & 0x1f; | ||
1828 | } | ||
1829 | static inline u32 fb_mmu_cbc_base_r(void) | ||
1830 | { | ||
1831 | return 0x00100ec4; | ||
1832 | } | ||
1833 | static inline u32 fb_mmu_cbc_base_address_f(u32 v) | ||
1834 | { | ||
1835 | return (v & 0x3ffffff) << 0; | ||
1836 | } | ||
1837 | static inline u32 fb_mmu_cbc_base_address_v(u32 r) | ||
1838 | { | ||
1839 | return (r >> 0) & 0x3ffffff; | ||
1840 | } | ||
1841 | static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) | ||
1842 | { | ||
1843 | return 0x0000000b; | ||
1844 | } | ||
1845 | static inline u32 fb_mmu_cbc_top_r(void) | ||
1846 | { | ||
1847 | return 0x00100ec8; | ||
1848 | } | ||
1849 | static inline u32 fb_mmu_cbc_top_size_f(u32 v) | ||
1850 | { | ||
1851 | return (v & 0x7fff) << 0; | ||
1852 | } | ||
1853 | static inline u32 fb_mmu_cbc_top_size_v(u32 r) | ||
1854 | { | ||
1855 | return (r >> 0) & 0x7fff; | ||
1856 | } | ||
1857 | static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) | ||
1858 | { | ||
1859 | return 0x0000000b; | ||
1860 | } | ||
1861 | static inline u32 fb_mmu_cbc_max_r(void) | ||
1862 | { | ||
1863 | return 0x00100ecc; | ||
1864 | } | ||
1865 | static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) | ||
1866 | { | ||
1867 | return (v & 0xffffff) << 0; | ||
1868 | } | ||
1869 | static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) | ||
1870 | { | ||
1871 | return (r >> 0) & 0xffffff; | ||
1872 | } | ||
1873 | static inline u32 fb_mmu_cbc_max_safe_f(u32 v) | ||
1874 | { | ||
1875 | return (v & 0x1) << 30; | ||
1876 | } | ||
1877 | static inline u32 fb_mmu_cbc_max_safe_true_v(void) | ||
1878 | { | ||
1879 | return 0x00000001; | ||
1880 | } | ||
1881 | static inline u32 fb_mmu_cbc_max_safe_false_v(void) | ||
1882 | { | ||
1883 | return 0x00000000; | ||
1884 | } | ||
1885 | static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v) | ||
1886 | { | ||
1887 | return (v & 0x1) << 31; | ||
1888 | } | ||
1889 | static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void) | ||
1890 | { | ||
1891 | return 0x00000000; | ||
1892 | } | ||
1893 | static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void) | ||
1894 | { | ||
1895 | return 0x00000001; | ||
1896 | } | ||
1817 | #endif | 1897 | #endif |