gpu: nvgpu: common: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I18cf871f2d1296b931d6ab43f1ac668551171dcc
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805076
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 79 insertions, 43 deletions

diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
index c790e297..bb99e644 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
@@ -63,16 +63,17 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
                          GCPLEX_CONFIG_WPR_ENABLED_MASK) &&
                         !(gcplex_config &
                                 GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) {
-                        if (gk20a_readl(g, fuse_opt_sec_debug_en_r()))
+                        if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) {
                                 nvgpu_log(g, gpu_dbg_info,
                                                 "gcplex_config = 0x%08x, "
                                                 "secure mode: ACR debug",
                                                 gcplex_config);
-                        else
+                        } else {
                                 nvgpu_log(g, gpu_dbg_info,
                                                 "gcplex_config = 0x%08x, "
                                                 "secure mode: ACR non debug",
                                                 gcplex_config);
+                        }
                 } else {
                         nvgpu_err(g, "gcplex_config = 0x%08x "
                                 "invalid wpr_enabled/vpr_auto_fetch_disable "
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
index 3a26e1b9..97570f9c 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
@@ -63,16 +63,17 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
                          GCPLEX_CONFIG_WPR_ENABLED_MASK) &&
                         !(gcplex_config &
                                 GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) {
-                        if (gk20a_readl(g, fuse_opt_sec_debug_en_r()))
+                        if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) {
                                 nvgpu_log(g, gpu_dbg_info,
                                                 "gcplex_config = 0x%08x, "
                                                 "secure mode: ACR debug",
                                                 gcplex_config);
-                        else
+                        } else {
                                 nvgpu_log(g, gpu_dbg_info,
                                                 "gcplex_config = 0x%08x, "
                                                 "secure mode: ACR non debug",
                                                 gcplex_config);
+                        }
 
                 } else {
                         nvgpu_err(g, "gcplex_config = 0x%08x "
diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c
index 28d63e82..623b0935 100644
--- a/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c
@@ -61,11 +61,13 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
 
         nvgpu_log_fn(g, " ");
 
-        if (max_comptag_lines == 0U)
+        if (max_comptag_lines == 0U) {
                 return 0;
+        }
 
-        if (max_comptag_lines > hw_max_comptag_lines)
+        if (max_comptag_lines > hw_max_comptag_lines) {
                 max_comptag_lines = hw_max_comptag_lines;
+        }
 
         compbit_backing_size =
                 DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) *
@@ -82,8 +84,9 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
                 (compbit_backing_size * comptags_per_cacheline) /
                 (gr->cacheline_size * gr->slices_per_ltc * g->ltc_count);
 
-        if (max_comptag_lines > hw_max_comptag_lines)
+        if (max_comptag_lines > hw_max_comptag_lines) {
                 max_comptag_lines = hw_max_comptag_lines;
+        }
 
         nvgpu_log_info(g, "compbit backing store size : %d",
                 compbit_backing_size);
@@ -91,12 +94,14 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
                 max_comptag_lines);
 
         err = nvgpu_ltc_alloc_cbc(g, compbit_backing_size);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = gk20a_comptag_allocator_init(g, &gr->comp_tags, max_comptag_lines);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         gr->max_comptag_lines = max_comptag_lines;
         gr->comptags_per_cacheline = comptags_per_cacheline;
@@ -121,8 +126,9 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
 
         trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max);
 
-        if (gr->compbit_store.mem.size == 0)
+        if (gr->compbit_store.mem.size == 0) {
                 return 0;
+        }
 
         while (1) {
                 const u32 iter_max = min(min + max_lines - 1, max);
@@ -168,8 +174,9 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
                                                    NVGPU_TIMER_RETRY_TIMER);
                                 do {
                                         val = gk20a_readl(g, ctrl1);
-                                        if (!(val & hw_op))
+                                        if (!(val & hw_op)) {
                                                 break;
+                                        }
                                         nvgpu_udelay(5);
                                 } while (!nvgpu_timeout_expired(&timeout));
 
@@ -182,8 +189,9 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
                 }
 
                 /* are we done? */
-                if (full_cache_op || iter_max == max)
+                if (full_cache_op || iter_max == max) {
                         break;
+                }
 
                 /* note: iter_max is inclusive upper bound */
                 min = iter_max + 1;
@@ -240,8 +248,9 @@ void gm20b_ltc_isr(struct gk20a *g)
         mc_intr = gk20a_readl(g, mc_intr_ltc_r());
         nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr);
         for (ltc = 0; ltc < g->ltc_count; ltc++) {
-                if ((mc_intr & 1U << ltc) == 0)
+                if ((mc_intr & 1U << ltc) == 0) {
                         continue;
+                }
                 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) {
                         ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() +
                                            ltc_stride * ltc +
@@ -433,12 +442,13 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
         u64 compbit_store_iova;
         u64 compbit_base_post_divide64;
 
-        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
+        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 compbit_store_iova = nvgpu_mem_get_phys_addr(g,
                                                         &gr->compbit_store.mem);
-        else
+        } else {
                 compbit_store_iova = nvgpu_mem_get_addr(g,
                                                         &gr->compbit_store.mem);
+        }
 
         compbit_base_post_divide64 = compbit_store_iova >>
                 ltc_ltcs_ltss_cbc_base_alignment_shift_v();
@@ -449,13 +459,15 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
         compbit_base_post_multiply64 = ((u64)compbit_base_post_divide *
                 g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v();
 
-        if (compbit_base_post_multiply64 < compbit_store_iova)
+        if (compbit_base_post_multiply64 < compbit_store_iova) {
                 compbit_base_post_divide++;
+        }
 
         /* Bug 1477079 indicates sw adjustment on the posted divided base. */
-        if (g->ops.ltc.cbc_fix_config)
+        if (g->ops.ltc.cbc_fix_config) {
                 compbit_base_post_divide =
                         g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide);
+        }
 
         gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(),
                 compbit_base_post_divide);
@@ -478,12 +490,13 @@ void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled)
         u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
         u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r());
 
-        if (enabled)
-                /* bypass disabled (normal caching ops)*/
+        if (enabled) {
+                /* bypass disabled (normal caching ops) */
                 reg &= ~reg_f;
-        else
+        } else {
                 /* bypass enabled (no caching) */
                 reg |= reg_f;
+        }
 
         gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
 }
diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c
index 5d0a8850..b72346ee 100644
--- a/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c
+++ b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c
@@ -83,15 +83,18 @@ int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
 
         nvgpu_log_fn(g, " ");
 
-        if (max_comptag_lines == 0U)
+        if (max_comptag_lines == 0U) {
                 return 0;
+        }
 
         /* Already initialized */
-        if (gr->max_comptag_lines)
+        if (gr->max_comptag_lines) {
                 return 0;
+        }
 
-        if (max_comptag_lines > hw_max_comptag_lines)
+        if (max_comptag_lines > hw_max_comptag_lines) {
                 max_comptag_lines = hw_max_comptag_lines;
+        }
 
         compbit_backing_size =
                 roundup(max_comptag_lines * gobs_per_comptagline_per_slice,
@@ -115,12 +118,14 @@ int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
                 gobs_per_comptagline_per_slice);
 
         err = nvgpu_ltc_alloc_cbc(g, compbit_backing_size);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = gk20a_comptag_allocator_init(g, &gr->comp_tags, max_comptag_lines);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         gr->max_comptag_lines = max_comptag_lines;
         gr->comptags_per_cacheline = comptags_per_cacheline;
@@ -146,8 +151,9 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
 
         trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max);
 
-        if (gr->compbit_store.mem.size == 0U)
+        if (gr->compbit_store.mem.size == 0U) {
                 return 0;
+        }
 
         while (1) {
                 const u32 iter_max = min(min + max_lines - 1, max);
@@ -195,8 +201,9 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
                                                    NVGPU_TIMER_RETRY_TIMER);
                                 do {
                                         val = gk20a_readl(g, ctrl1);
-                                        if (!(val & hw_op))
+                                        if (!(val & hw_op)) {
                                                 break;
+                                        }
                                         nvgpu_udelay(5);
                                 } while (!nvgpu_timeout_expired(&timeout));
 
@@ -209,8 +216,9 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
                 }
 
                 /* are we done? */
-                if (full_cache_op || iter_max == max)
+                if (full_cache_op || iter_max == max) {
                         break;
+                }
 
                 /* note: iter_max is inclusive upper bound */
                 min = iter_max + 1;
@@ -234,8 +242,9 @@ void gp10b_ltc_isr(struct gk20a *g)
         mc_intr = gk20a_readl(g, mc_intr_ltc_r());
         nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr);
         for (ltc = 0; ltc < g->ltc_count; ltc++) {
-                if ((mc_intr & 1U << ltc) == 0)
+                if ((mc_intr & 1U << ltc) == 0) {
                         continue;
+                }
                 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) {
                         u32 offset = ltc_stride * ltc + lts_stride * slice;
                         ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset);
@@ -310,12 +319,13 @@ void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled)
         u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
         u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r());
 
-        if (enabled)
-                /* bypass disabled (normal caching ops)*/
+        if (enabled) {
+                /* bypass disabled (normal caching ops) */
                 reg &= ~reg_f;
-        else
+        } else {
                 /* bypass enabled (no caching) */
                 reg |= reg_f;
+        }
 
         nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
 }
diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c
index 04525375..53141c9a 100644
--- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c
+++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c
@@ -75,24 +75,28 @@ void gp10b_priv_ring_decode_error_code(struct gk20a *g,
 
         if (error_code == 0xBADF1000) {
                 if (error_type_index <
-                                ARRAY_SIZE(error_type_badf1xyy))
+                                ARRAY_SIZE(error_type_badf1xyy)) {
                         nvgpu_err(g, "%s",
                                 error_type_badf1xyy[error_type_index]);
+                }
         } else if (error_code == 0xBADF2000) {
                 if (error_type_index <
-                                ARRAY_SIZE(error_type_badf2xyy))
+                                ARRAY_SIZE(error_type_badf2xyy)) {
                         nvgpu_err(g, "%s",
                                 error_type_badf2xyy[error_type_index]);
+                }
         } else if (error_code == 0xBADF3000) {
                 if (error_type_index <
-                                ARRAY_SIZE(error_type_badf3xyy))
+                                ARRAY_SIZE(error_type_badf3xyy)) {
                         nvgpu_err(g, "%s",
                                 error_type_badf3xyy[error_type_index]);
+                }
         } else if (error_code == 0xBADF5000) {
                 if (error_type_index <
-                                ARRAY_SIZE(error_type_badf5xyy))
+                                ARRAY_SIZE(error_type_badf5xyy)) {
                         nvgpu_err(g, "%s",
                                 error_type_badf5xyy[error_type_index]);
+                }
         }
 }
 
@@ -117,15 +121,18 @@ void gp10b_priv_ring_isr(struct gk20a *g)
         nvgpu_err(g, "ringmaster intr status0: 0x%08x,"
                 "status1: 0x%08x", status0, status1);
 
-        if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0)
+        if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0) {
                 nvgpu_err(g,
                         "BUG: connectivity problem on the startup sequence");
+        }
 
-        if (pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0)
+        if (pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0) {
                 nvgpu_err(g, "ring disconnected");
+        }
 
-        if (pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0)
+        if (pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) {
                 nvgpu_err(g, "ring overflowed");
+        }
 
         if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
                 error_info =
@@ -141,8 +148,9 @@ void gp10b_priv_ring_isr(struct gk20a *g)
                         pri_ringstation_sys_priv_error_info_subid_v(error_info),
                         pri_ringstation_sys_priv_error_info_priv_level_v(error_info),
                         error_code);
-                if (g->ops.priv_ring.decode_error_code)
+                if (g->ops.priv_ring.decode_error_code) {
                         g->ops.priv_ring.decode_error_code(g, error_code);
+                }
         }
 
         if (status1) {
@@ -167,13 +175,15 @@ void gp10b_priv_ring_isr(struct gk20a *g)
                                         pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info),
                                         error_code);
 
-                                if (g->ops.priv_ring.decode_error_code)
+                                if (g->ops.priv_ring.decode_error_code) {
                                         g->ops.priv_ring.decode_error_code(g,
                                                                 error_code);
+                                }
 
                                 status1 = status1 & (~(BIT(gpc)));
-                                if (!status1)
+                                if (!status1) {
                                         break;
+                                }
                         }
                 }
         }
@@ -193,6 +203,7 @@ void gp10b_priv_ring_isr(struct gk20a *g)
                 retry--;
         }
 
-        if (retry == 0)
+        if (retry == 0) {
                 nvgpu_err(g, "priv ringmaster intr ack failed");
+        }
 }