gpu: nvgpu: Add struct gk20a ptr to FUSE APIs

Add a pointer to struct gk20a to the FUSE APIs. This helps
QNX builds avoid any static data definitions.

Also this change plumbs struct gk20a in some of the Linux clk
code and fixes a few minor style nits.

Change-Id: I27dfb2c4e9a352f784d6cead150460d8e9e808d3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537611
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

7 files changed, 44 insertions, 43 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/fuse.c b/drivers/gpu/nvgpu/common/linux/fuse.c
index 993cbc5a..27851f92 100644
--- a/drivers/gpu/nvgpu/common/linux/fuse.c
+++ b/drivers/gpu/nvgpu/common/linux/fuse.c
@@ -15,7 +15,7 @@
 
 #include <nvgpu/fuse.h>
 
-int nvgpu_tegra_get_gpu_speedo_id(void)
+int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g)
 {
         return tegra_sku_info.gpu_speedo_id;
 }
@@ -24,32 +24,32 @@ int nvgpu_tegra_get_gpu_speedo_id(void)
  * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
  * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
  */
-void nvgpu_tegra_fuse_write_bypass(u32 val)
+void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
 {
         tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0);
 }
 
-void nvgpu_tegra_fuse_write_access_sw(u32 val)
+void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
 {
         tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0);
 }
 
-void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val)
+void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
 {
         tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0);
 }
 
-void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val)
+void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
 {
         tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
 }
 
-int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val)
+int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
 {
         return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
 }
 
-int nvgpu_tegra_fuse_read_reserved_calib(u32 *val)
+int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
 {
         return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
 }
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index 22501c64..027d4fb6 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -258,12 +258,13 @@ static inline int fuse_get_gpcpll_adc_intercept_uv(u32 val)
         return ((val >> 4) & 0x3ff) * 1000 + ((val >> 0) & 0xf) * 100;
 }
 
-static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv)
+static int nvgpu_fuse_calib_gpcpll_get_adc(struct gk20a *g,
+                                           int *slope_uv, int *intercept_uv)
 {
         u32 val;
         int ret;
 
-        ret = nvgpu_tegra_fuse_read_reserved_calib(&val);
+        ret = nvgpu_tegra_fuse_read_reserved_calib(g, &val);
         if (ret)
                 return ret;
 
@@ -276,9 +277,9 @@ static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv)
 }
 
 #ifdef CONFIG_TEGRA_USE_NA_GPCPLL
-static bool nvgpu_fuse_can_use_na_gpcpll(void)
+static bool nvgpu_fuse_can_use_na_gpcpll(struct gk20a *g)
 {
-        return nvgpu_tegra_get_gpu_speedo_id();
+        return nvgpu_tegra_get_gpu_speedo_id(g);
 }
 #endif
 
@@ -291,7 +292,7 @@ static int clk_config_calibration_params(struct gk20a *g)
         int slope, offs;
         struct pll_parms *p = &gpc_pll_params;
 
-        if (!nvgpu_fuse_calib_gpcpll_get_adc(&slope, &offs)) {
+        if (!nvgpu_fuse_calib_gpcpll_get_adc(g, &slope, &offs)) {
                 p->uvdet_slope = slope;
                 p->uvdet_offs = offs;
         }
@@ -1186,7 +1187,7 @@ int gm20b_init_clk_setup_sw(struct gk20a *g)
           */
         clk_config_calibration_params(g);
 #ifdef CONFIG_TEGRA_USE_NA_GPCPLL
-        if (nvgpu_fuse_can_use_na_gpcpll()) {
+        if (nvgpu_fuse_can_use_na_gpcpll(g)) {
                 /* NA mode is supported only at max update rate 38.4 MHz */
                 BUG_ON(clk->gpc_pll.clk_in != gpc_pll_params.max_u);
                 clk->gpc_pll.mode = GPC_PLL_MODE_DVFS;
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index f60d880d..87cf3f01 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -548,18 +548,18 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 
 static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
-        nvgpu_tegra_fuse_write_bypass(0x1);
-        nvgpu_tegra_fuse_write_access_sw(0x0);
+        nvgpu_tegra_fuse_write_bypass(g, 0x1);
+        nvgpu_tegra_fuse_write_access_sw(g, 0x0);
 
         if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) {
-                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0);
-                nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x1);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(g, 0x1);
         } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) {
-                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1);
-                nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(g, 0x0);
         } else {
-                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0);
-                nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(g, 0x0);
         }
 }
 
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 98cd3906..b85e72a0 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -265,13 +265,12 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g)
 {
         u32 val;
 
-        nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x",
+        nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x",
                         gk20a_readl(g, fuse_opt_sec_debug_en_r()));
-        nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
+        nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x",
                         gk20a_readl(g, fuse_opt_priv_sec_en_r()));
-        nvgpu_tegra_fuse_read_gcplex_config_fuse(&val);
-        nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
-                        val);
+        nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val);
+        nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val);
 }
 
 void gm20b_init_pmu_ops(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index d2b86e51..05fbeb21 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1600,15 +1600,15 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g)
 
 static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
-        nvgpu_tegra_fuse_write_bypass(0x1);
-        nvgpu_tegra_fuse_write_access_sw(0x0);
+        nvgpu_tegra_fuse_write_bypass(g, 0x1);
+        nvgpu_tegra_fuse_write_access_sw(g, 0x0);
 
         if (g->gr.gpc_tpc_mask[gpc_index] == 0x1)
-                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x2);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2);
         else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2)
-                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1);
         else
-                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0);
+                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0);
 }
 
 static void gr_gp10b_get_access_map(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index e9a9b922..da8044cd 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -378,13 +378,12 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g)
 {
         u32 val;
 
-        nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x",
+        nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x",
                         gk20a_readl(g, fuse_opt_sec_debug_en_r()));
-        nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
+        nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x",
                         gk20a_readl(g, fuse_opt_priv_sec_en_r()));
-        nvgpu_tegra_fuse_read_gcplex_config_fuse(&val);
-        nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
-                        val);
+        nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val);
+        nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val);
 }
 
 static bool gp10b_is_pmu_supported(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
index 3650fd58..c10ece1d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fuse.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
@@ -13,13 +13,15 @@
 #ifndef __NVGPU_FUSE_H__
 #define __NVGPU_FUSE_H__
 
-int nvgpu_tegra_get_gpu_speedo_id(void);
+struct gk20a;
 
-void nvgpu_tegra_fuse_write_bypass(u32 val);
-void nvgpu_tegra_fuse_write_access_sw(u32 val);
-void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val);
-void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val);
-int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val);
-int nvgpu_tegra_fuse_read_reserved_calib(u32 *val);
+int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g);
+
+void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val);
+void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val);
+void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val);
+void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val);
+int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
+int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val);
 
 #endif