gpu: nvgpu: Do not leak ACR header

4b6f83704f054f5b21e05873fa5862c667a9992e tried to fix ACR related
leak. It fell short, because the data structures related were local
and thus the leak was not really fixed.

This patch stores the ACR ucode blob in a global variable, which
survives across rail gating.

Change-Id: Iec3ac9d41156baa26048e079732568c0a95264f4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/733732
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>

2 files changed, 7 insertions, 12 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 1e07f139..2e33c3f0 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -216,7 +216,7 @@ int prepare_ucode_blob(struct gk20a *g)
         struct ls_flcn_mgr lsfm_l, *plsfm;
         struct pmu_gk20a *pmu = &g->pmu;
 
-        if (g->acr.ucode_blob_start) {
+        if (g->acr.ucode_blob.cpu_va) {
                 /*Recovery case, we do not need to form
                 non WPR blob of ucodes*/
                 err = gk20a_init_pmu(pmu);
@@ -238,23 +238,20 @@ int prepare_ucode_blob(struct gk20a *g)
         if (err)
                 return err;
 
-        if (plsfm->managed_flcn_cnt && !plsfm->mem.cpu_va) {
+        if (plsfm->managed_flcn_cnt && !g->acr.ucode_blob.cpu_va) {
                 /* Generate WPR requirements*/
                 err = lsf_gen_wpr_requirements(g, plsfm);
                 if (err)
                         return err;
 
                 /*Alloc memory to hold ucode blob contents*/
-                err = gk20a_gmmu_alloc(g, plsfm->wpr_size, &plsfm->mem);
+                err = gk20a_gmmu_alloc(g, plsfm->wpr_size, &g->acr.ucode_blob);
                 if (err)
                         return err;
 
                 gm20b_dbg_pmu("managed LS falcon %d, WPR size %d bytes.\n",
                         plsfm->managed_flcn_cnt, plsfm->wpr_size);
-                lsfm_init_wpr_contents(g, plsfm, plsfm->mem.cpu_va);
-                g->acr.ucode_blob_start = g->ops.mm.get_iova_addr(g,
-                                plsfm->mem.sgt->sgl, 0);
-                g->acr.ucode_blob_size = plsfm->wpr_size;
+                lsfm_init_wpr_contents(g, plsfm, g->acr.ucode_blob.cpu_va);
         } else {
                 gm20b_dbg_pmu("LSFM is managing no falcons.\n");
         }
@@ -880,8 +877,8 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g)
         u32 *acr_ucode_header_t210_load;
         u32 *acr_ucode_data_t210_load;
 
-        start = acr->ucode_blob_start;
-        size = acr->ucode_blob_size;
+        start = g->ops.mm.get_iova_addr(g, acr->ucode_blob.sgt->sgl, 0);
+        size = acr->ucode_blob.size;
 
         gm20b_dbg_pmu("");
 
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index 557acbc7..8970bf55 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -259,7 +259,6 @@ struct lsfm_managed_ucode_img {
 struct ls_flcn_mgr {
         u16 managed_flcn_cnt;
         u32 wpr_size;
-        struct mem_desc mem;
         u32 disable_mask;
         struct lsfm_managed_ucode_img *ucode_img_list;
         void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
@@ -373,8 +372,7 @@ struct acr_fw_header {
 };
 
 struct acr_gm20b {
-        u64 ucode_blob_start;
-        u32 ucode_blob_size;
+        struct mem_desc ucode_blob;
         struct bin_hdr *bl_bin_hdr;
         struct hsflcn_bl_desc *pmu_hsbl_desc;
         struct bin_hdr *hsbin_hdr;