diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-04-27 12:32:04 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-02 19:05:46 -0400 |
commit | 2e131a1e10a6e62fe6861f2893050e6ea2cf5239 (patch) | |
tree | 92c65104d57db7c9813be5964bb97374d38f9d98 /drivers/gpu/nvgpu | |
parent | ed60c25d3840c9d198e7b4b5f852382b02ed64bd (diff) |
gpu: nvgpu: remove gk20a_reset_priv_ring
gk20a_reset_priv_ring does not help resetting priv ring.
Chip reset is the only way to recover.
Bug 200300756
Change-Id: Ia913d46b0e71cd42e9ce242b2393c50f4d12e002
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1471445
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index 1584ffda..96e21d2d 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -45,27 +45,6 @@ void gk20a_enable_priv_ring(struct gk20a *g) | |||
45 | 45 | ||
46 | } | 46 | } |
47 | 47 | ||
48 | static void gk20a_reset_priv_ring(struct gk20a *g) | ||
49 | { | ||
50 | u32 val; | ||
51 | |||
52 | g->ops.mc.reset(g, mc_enable_priv_ring_enabled_f()); | ||
53 | |||
54 | val = gk20a_readl(g, pri_ringstation_sys_decode_config_r()); | ||
55 | val = set_field(val, | ||
56 | pri_ringstation_sys_decode_config_ring_m(), | ||
57 | pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()); | ||
58 | gk20a_writel(g, pri_ringstation_sys_decode_config_r(), val); | ||
59 | |||
60 | gk20a_writel(g, pri_ringmaster_global_ctl_r(), | ||
61 | pri_ringmaster_global_ctl_ring_reset_asserted_f()); | ||
62 | nvgpu_udelay(20); | ||
63 | gk20a_writel(g, pri_ringmaster_global_ctl_r(), | ||
64 | pri_ringmaster_global_ctl_ring_reset_deasserted_f()); | ||
65 | |||
66 | gk20a_enable_priv_ring(g); | ||
67 | } | ||
68 | |||
69 | void gk20a_priv_ring_isr(struct gk20a *g) | 48 | void gk20a_priv_ring_isr(struct gk20a *g) |
70 | { | 49 | { |
71 | u32 status0, status1; | 50 | u32 status0, status1; |
@@ -83,12 +62,6 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
83 | gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x," | 62 | gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x," |
84 | "status1: 0x%08x", status0, status1); | 63 | "status1: 0x%08x", status0, status1); |
85 | 64 | ||
86 | if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0 || | ||
87 | pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0 || | ||
88 | pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) { | ||
89 | gk20a_reset_priv_ring(g); | ||
90 | } | ||
91 | |||
92 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { | 65 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { |
93 | gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", | 66 | gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", |
94 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), | 67 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), |