gpu: nvgpu: resolve MISRA 10.3 violations

MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was
assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This
value was then returned in a function defined by gpu_ops.

This patch changes the return type for these gpu_ops to u64 and updates
the functions that implement the functions and lastly the saved value. This
removes the violation in this instance.

JIRA NVGPU-647

Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805588
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

11 files changed, 101 insertions, 101 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 5a888303..e51d768b 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1124,20 +1124,20 @@ struct gpu_ops {
                             u64 num_ops);
                 const struct regop_offset_range* (
                                 *get_global_whitelist_ranges)(void);
-                int (*get_global_whitelist_ranges_count)(void);
+                u64 (*get_global_whitelist_ranges_count)(void);
                 const struct regop_offset_range* (
                                 *get_context_whitelist_ranges)(void);
-                int (*get_context_whitelist_ranges_count)(void);
+                u64 (*get_context_whitelist_ranges_count)(void);
                 const u32* (*get_runcontrol_whitelist)(void);
-                int (*get_runcontrol_whitelist_count)(void);
+                u64 (*get_runcontrol_whitelist_count)(void);
                 const struct regop_offset_range* (
                                 *get_runcontrol_whitelist_ranges)(void);
-                int (*get_runcontrol_whitelist_ranges_count)(void);
+                u64 (*get_runcontrol_whitelist_ranges_count)(void);
                 const u32* (*get_qctl_whitelist)(void);
-                int (*get_qctl_whitelist_count)(void);
+                u64 (*get_qctl_whitelist_count)(void);
                 const struct regop_offset_range* (
                                 *get_qctl_whitelist_ranges)(void);
-                int (*get_qctl_whitelist_ranges_count)(void);
+                u64 (*get_qctl_whitelist_ranges_count)(void);
                 int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s);
         } regops;
         struct {
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
index aaa055b6..e23a0a62 100644
--- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2013-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -261,7 +261,7 @@ static const struct regop_offset_range gm20b_global_whitelist_ranges[] = {
         { 0x00504eb0,   1 },
         { 0x00504ef0,  28 },
 };
-static const u32 gm20b_global_whitelist_ranges_count =
+static const u64 gm20b_global_whitelist_ranges_count =
         ARRAY_SIZE(gm20b_global_whitelist_ranges);
 
 /* context */
@@ -351,7 +351,7 @@ static const struct regop_offset_range gm20b_context_whitelist_ranges[] = {
         { 0x00504ee8,   1 },
         { 0x00504ef0,  28 },
 };
-static const u32 gm20b_context_whitelist_ranges_count =
+static const u64 gm20b_context_whitelist_ranges_count =
         ARRAY_SIZE(gm20b_context_whitelist_ranges);
 
 /* runcontrol */
@@ -363,7 +363,7 @@ static const u32 gm20b_runcontrol_whitelist[] = {
         0x00504610,
         0x00504e10,
 };
-static const u32 gm20b_runcontrol_whitelist_count =
+static const u64 gm20b_runcontrol_whitelist_count =
         ARRAY_SIZE(gm20b_runcontrol_whitelist);
 
 static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = {
@@ -374,19 +374,19 @@ static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = {
         { 0x00504610,   1 },
         { 0x00504e10,   1 },
 };
-static const u32 gm20b_runcontrol_whitelist_ranges_count =
+static const u64 gm20b_runcontrol_whitelist_ranges_count =
         ARRAY_SIZE(gm20b_runcontrol_whitelist_ranges);
 
 
 /* quad ctl */
 static const u32 gm20b_qctl_whitelist[] = {
 };
-static const u32 gm20b_qctl_whitelist_count =
+static const u64 gm20b_qctl_whitelist_count =
         ARRAY_SIZE(gm20b_qctl_whitelist);
 
 static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = {
 };
-static const u32 gm20b_qctl_whitelist_ranges_count =
+static const u64 gm20b_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gm20b_qctl_whitelist_ranges);
 
 const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void)
@@ -394,7 +394,7 @@ const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void)
         return gm20b_global_whitelist_ranges;
 }
 
-int gm20b_get_global_whitelist_ranges_count(void)
+u64 gm20b_get_global_whitelist_ranges_count(void)
 {
         return gm20b_global_whitelist_ranges_count;
 }
@@ -404,7 +404,7 @@ const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void)
         return gm20b_context_whitelist_ranges;
 }
 
-int gm20b_get_context_whitelist_ranges_count(void)
+u64 gm20b_get_context_whitelist_ranges_count(void)
 {
         return gm20b_context_whitelist_ranges_count;
 }
@@ -414,7 +414,7 @@ const u32 *gm20b_get_runcontrol_whitelist(void)
         return gm20b_runcontrol_whitelist;
 }
 
-int gm20b_get_runcontrol_whitelist_count(void)
+u64 gm20b_get_runcontrol_whitelist_count(void)
 {
         return gm20b_runcontrol_whitelist_count;
 }
@@ -424,7 +424,7 @@ const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void)
         return gm20b_runcontrol_whitelist_ranges;
 }
 
-int gm20b_get_runcontrol_whitelist_ranges_count(void)
+u64 gm20b_get_runcontrol_whitelist_ranges_count(void)
 {
         return gm20b_runcontrol_whitelist_ranges_count;
 }
@@ -434,7 +434,7 @@ const u32 *gm20b_get_qctl_whitelist(void)
         return gm20b_qctl_whitelist;
 }
 
-int gm20b_get_qctl_whitelist_count(void)
+u64 gm20b_get_qctl_whitelist_count(void)
 {
         return gm20b_qctl_whitelist_count;
 }
@@ -444,7 +444,7 @@ const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void)
         return gm20b_qctl_whitelist_ranges;
 }
 
-int gm20b_get_qctl_whitelist_ranges_count(void)
+u64 gm20b_get_qctl_whitelist_ranges_count(void)
 {
         return gm20b_qctl_whitelist_ranges_count;
 }
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h
index f0246e0e..99044f09 100644
--- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h
@@ -2,7 +2,7 @@
  *
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2018 NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,17 +28,17 @@
 struct dbg_session_gk20a;
 
 const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void);
-int gm20b_get_global_whitelist_ranges_count(void);
+u64 gm20b_get_global_whitelist_ranges_count(void);
 const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void);
-int gm20b_get_context_whitelist_ranges_count(void);
+u64 gm20b_get_context_whitelist_ranges_count(void);
 const u32 *gm20b_get_runcontrol_whitelist(void);
-int gm20b_get_runcontrol_whitelist_count(void);
+u64 gm20b_get_runcontrol_whitelist_count(void);
 const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void);
-int gm20b_get_runcontrol_whitelist_ranges_count(void);
+u64 gm20b_get_runcontrol_whitelist_ranges_count(void);
 const u32 *gm20b_get_qctl_whitelist(void);
-int gm20b_get_qctl_whitelist_count(void);
+u64 gm20b_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void);
-int gm20b_get_qctl_whitelist_ranges_count(void);
+u64 gm20b_get_qctl_whitelist_ranges_count(void);
 int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* __REGOPS_GM20B_H_ */
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.c b/drivers/gpu/nvgpu/gp106/regops_gp106.c
index d9dadbac..25b88eeb 100644
--- a/drivers/gpu/nvgpu/gp106/regops_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/regops_gp106.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GP106 GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1686,7 +1686,7 @@ static const struct regop_offset_range gp106_global_whitelist_ranges[] = {
 };
 
 
-static const u32 gp106_global_whitelist_ranges_count =
+static const u64 gp106_global_whitelist_ranges_count =
         ARRAY_SIZE(gp106_global_whitelist_ranges);
 
 /* context */
@@ -1694,24 +1694,24 @@ static const u32 gp106_global_whitelist_ranges_count =
 /* runcontrol */
 static const u32 gp106_runcontrol_whitelist[] = {
 };
-static const u32 gp106_runcontrol_whitelist_count =
+static const u64 gp106_runcontrol_whitelist_count =
         ARRAY_SIZE(gp106_runcontrol_whitelist);
 
 static const struct regop_offset_range gp106_runcontrol_whitelist_ranges[] = {
 };
-static const u32 gp106_runcontrol_whitelist_ranges_count =
+static const u64 gp106_runcontrol_whitelist_ranges_count =
         ARRAY_SIZE(gp106_runcontrol_whitelist_ranges);
 
 
 /* quad ctl */
 static const u32 gp106_qctl_whitelist[] = {
 };
-static const u32 gp106_qctl_whitelist_count =
+static const u64 gp106_qctl_whitelist_count =
         ARRAY_SIZE(gp106_qctl_whitelist);
 
 static const struct regop_offset_range gp106_qctl_whitelist_ranges[] = {
 };
-static const u32 gp106_qctl_whitelist_ranges_count =
+static const u64 gp106_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gp106_qctl_whitelist_ranges);
 
 const struct regop_offset_range *gp106_get_global_whitelist_ranges(void)
@@ -1719,7 +1719,7 @@ const struct regop_offset_range *gp106_get_global_whitelist_ranges(void)
         return gp106_global_whitelist_ranges;
 }
 
-int gp106_get_global_whitelist_ranges_count(void)
+u64 gp106_get_global_whitelist_ranges_count(void)
 {
         return gp106_global_whitelist_ranges_count;
 }
@@ -1729,7 +1729,7 @@ const struct regop_offset_range *gp106_get_context_whitelist_ranges(void)
         return gp106_global_whitelist_ranges;
 }
 
-int gp106_get_context_whitelist_ranges_count(void)
+u64 gp106_get_context_whitelist_ranges_count(void)
 {
         return gp106_global_whitelist_ranges_count;
 }
@@ -1739,7 +1739,7 @@ const u32 *gp106_get_runcontrol_whitelist(void)
         return gp106_runcontrol_whitelist;
 }
 
-int gp106_get_runcontrol_whitelist_count(void)
+u64 gp106_get_runcontrol_whitelist_count(void)
 {
         return gp106_runcontrol_whitelist_count;
 }
@@ -1749,7 +1749,7 @@ const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void)
         return gp106_runcontrol_whitelist_ranges;
 }
 
-int gp106_get_runcontrol_whitelist_ranges_count(void)
+u64 gp106_get_runcontrol_whitelist_ranges_count(void)
 {
         return gp106_runcontrol_whitelist_ranges_count;
 }
@@ -1759,7 +1759,7 @@ const u32 *gp106_get_qctl_whitelist(void)
         return gp106_qctl_whitelist;
 }
 
-int gp106_get_qctl_whitelist_count(void)
+u64 gp106_get_qctl_whitelist_count(void)
 {
         return gp106_qctl_whitelist_count;
 }
@@ -1769,7 +1769,7 @@ const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void)
         return gp106_qctl_whitelist_ranges;
 }
 
-int gp106_get_qctl_whitelist_ranges_count(void)
+u64 gp106_get_qctl_whitelist_ranges_count(void)
 {
         return gp106_qctl_whitelist_ranges_count;
 }
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.h b/drivers/gpu/nvgpu/gp106/regops_gp106.h
index 801e6f1c..45f1fb49 100644
--- a/drivers/gpu/nvgpu/gp106/regops_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/regops_gp106.h
@@ -2,7 +2,7 @@
  *
  * Tegra GP106 GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,17 +26,17 @@
 #define __REGOPS_GP106_H_
 
 const struct regop_offset_range *gp106_get_global_whitelist_ranges(void);
-int gp106_get_global_whitelist_ranges_count(void);
+u64 gp106_get_global_whitelist_ranges_count(void);
 const struct regop_offset_range *gp106_get_context_whitelist_ranges(void);
-int gp106_get_context_whitelist_ranges_count(void);
+u64 gp106_get_context_whitelist_ranges_count(void);
 const u32 *gp106_get_runcontrol_whitelist(void);
-int gp106_get_runcontrol_whitelist_count(void);
+u64 gp106_get_runcontrol_whitelist_count(void);
 const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void);
-int gp106_get_runcontrol_whitelist_ranges_count(void);
+u64 gp106_get_runcontrol_whitelist_ranges_count(void);
 const u32 *gp106_get_qctl_whitelist(void);
-int gp106_get_qctl_whitelist_count(void);
+u64 gp106_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void);
-int gp106_get_qctl_whitelist_ranges_count(void);
+u64 gp106_get_qctl_whitelist_ranges_count(void);
 int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* __REGOPS_GP106_H_ */
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
index 60f36b6c..8113f7d5 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -382,7 +382,7 @@ static const struct regop_offset_range gp10b_global_whitelist_ranges[] = {
         { 0x009a0100,   1},
 };
 
-static const u32 gp10b_global_whitelist_ranges_count =
+static const u64 gp10b_global_whitelist_ranges_count =
         ARRAY_SIZE(gp10b_global_whitelist_ranges);
 
 /* context */
@@ -390,24 +390,24 @@ static const u32 gp10b_global_whitelist_ranges_count =
 /* runcontrol */
 static const u32 gp10b_runcontrol_whitelist[] = {
 };
-static const u32 gp10b_runcontrol_whitelist_count =
+static const u64 gp10b_runcontrol_whitelist_count =
         ARRAY_SIZE(gp10b_runcontrol_whitelist);
 
 static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = {
 };
-static const u32 gp10b_runcontrol_whitelist_ranges_count =
+static const u64 gp10b_runcontrol_whitelist_ranges_count =
         ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges);
 
 
 /* quad ctl */
 static const u32 gp10b_qctl_whitelist[] = {
 };
-static const u32 gp10b_qctl_whitelist_count =
+static const u64 gp10b_qctl_whitelist_count =
         ARRAY_SIZE(gp10b_qctl_whitelist);
 
 static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = {
 };
-static const u32 gp10b_qctl_whitelist_ranges_count =
+static const u64 gp10b_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gp10b_qctl_whitelist_ranges);
 
 const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
@@ -415,7 +415,7 @@ const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
         return gp10b_global_whitelist_ranges;
 }
 
-int gp10b_get_global_whitelist_ranges_count(void)
+u64 gp10b_get_global_whitelist_ranges_count(void)
 {
         return gp10b_global_whitelist_ranges_count;
 }
@@ -425,7 +425,7 @@ const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void)
         return gp10b_global_whitelist_ranges;
 }
 
-int gp10b_get_context_whitelist_ranges_count(void)
+u64 gp10b_get_context_whitelist_ranges_count(void)
 {
         return gp10b_global_whitelist_ranges_count;
 }
@@ -435,7 +435,7 @@ const u32 *gp10b_get_runcontrol_whitelist(void)
         return gp10b_runcontrol_whitelist;
 }
 
-int gp10b_get_runcontrol_whitelist_count(void)
+u64 gp10b_get_runcontrol_whitelist_count(void)
 {
         return gp10b_runcontrol_whitelist_count;
 }
@@ -445,7 +445,7 @@ const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void)
         return gp10b_runcontrol_whitelist_ranges;
 }
 
-int gp10b_get_runcontrol_whitelist_ranges_count(void)
+u64 gp10b_get_runcontrol_whitelist_ranges_count(void)
 {
         return gp10b_runcontrol_whitelist_ranges_count;
 }
@@ -455,7 +455,7 @@ const u32 *gp10b_get_qctl_whitelist(void)
         return gp10b_qctl_whitelist;
 }
 
-int gp10b_get_qctl_whitelist_count(void)
+u64 gp10b_get_qctl_whitelist_count(void)
 {
         return gp10b_qctl_whitelist_count;
 }
@@ -465,7 +465,7 @@ const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void)
         return gp10b_qctl_whitelist_ranges;
 }
 
-int gp10b_get_qctl_whitelist_ranges_count(void)
+u64 gp10b_get_qctl_whitelist_ranges_count(void)
 {
         return gp10b_qctl_whitelist_ranges_count;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
index 7bc08189..e8b9f325 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
@@ -2,7 +2,7 @@
  *
  * Tegra GP10B GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,17 +28,17 @@
 struct dbg_session_gk20a;
 
 const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void);
-int gp10b_get_global_whitelist_ranges_count(void);
+u64 gp10b_get_global_whitelist_ranges_count(void);
 const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void);
-int gp10b_get_context_whitelist_ranges_count(void);
+u64 gp10b_get_context_whitelist_ranges_count(void);
 const u32 *gp10b_get_runcontrol_whitelist(void);
-int gp10b_get_runcontrol_whitelist_count(void);
+u64 gp10b_get_runcontrol_whitelist_count(void);
 const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void);
-int gp10b_get_runcontrol_whitelist_ranges_count(void);
+u64 gp10b_get_runcontrol_whitelist_ranges_count(void);
 const u32 *gp10b_get_qctl_whitelist(void);
-int gp10b_get_qctl_whitelist_count(void);
+u64 gp10b_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void);
-int gp10b_get_qctl_whitelist_ranges_count(void);
+u64 gp10b_get_qctl_whitelist_ranges_count(void);
 int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* __REGOPS_GP10B_H_ */
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.c b/drivers/gpu/nvgpu/gv100/regops_gv100.c
index 857fc01d..c6ce6b94 100644
--- a/drivers/gpu/nvgpu/gv100/regops_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/regops_gv100.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GV100 GPU Driver Register Ops
  *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -5623,7 +5623,7 @@ static const struct regop_offset_range gv100_global_whitelist_ranges[] = {
         { 0x00a3eed4,   7},
         { 0x00a3eef4,   2}};
 
-static const u32 gv100_global_whitelist_ranges_count =
+static const u64 gv100_global_whitelist_ranges_count =
         ARRAY_SIZE(gv100_global_whitelist_ranges);
 
 /* context */
@@ -5631,24 +5631,24 @@ static const u32 gv100_global_whitelist_ranges_count =
 /* runcontrol */
 static const u32 gv100_runcontrol_whitelist[] = {
 };
-static const u32 gv100_runcontrol_whitelist_count =
+static const u64 gv100_runcontrol_whitelist_count =
         ARRAY_SIZE(gv100_runcontrol_whitelist);
 
 static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = {
 };
-static const u32 gv100_runcontrol_whitelist_ranges_count =
+static const u64 gv100_runcontrol_whitelist_ranges_count =
         ARRAY_SIZE(gv100_runcontrol_whitelist_ranges);
 
 
 /* quad ctl */
 static const u32 gv100_qctl_whitelist[] = {
 };
-static const u32 gv100_qctl_whitelist_count =
+static const u64 gv100_qctl_whitelist_count =
         ARRAY_SIZE(gv100_qctl_whitelist);
 
 static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = {
 };
-static const u32 gv100_qctl_whitelist_ranges_count =
+static const u64 gv100_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gv100_qctl_whitelist_ranges);
 
 const struct regop_offset_range *gv100_get_global_whitelist_ranges(void)
@@ -5656,7 +5656,7 @@ const struct regop_offset_range *gv100_get_global_whitelist_ranges(void)
         return gv100_global_whitelist_ranges;
 }
 
-int gv100_get_global_whitelist_ranges_count(void)
+u64 gv100_get_global_whitelist_ranges_count(void)
 {
         return gv100_global_whitelist_ranges_count;
 }
@@ -5666,7 +5666,7 @@ const struct regop_offset_range *gv100_get_context_whitelist_ranges(void)
         return gv100_global_whitelist_ranges;
 }
 
-int gv100_get_context_whitelist_ranges_count(void)
+u64 gv100_get_context_whitelist_ranges_count(void)
 {
         return gv100_global_whitelist_ranges_count;
 }
@@ -5676,7 +5676,7 @@ const u32 *gv100_get_runcontrol_whitelist(void)
         return gv100_runcontrol_whitelist;
 }
 
-int gv100_get_runcontrol_whitelist_count(void)
+u64 gv100_get_runcontrol_whitelist_count(void)
 {
         return gv100_runcontrol_whitelist_count;
 }
@@ -5686,7 +5686,7 @@ const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void)
         return gv100_runcontrol_whitelist_ranges;
 }
 
-int gv100_get_runcontrol_whitelist_ranges_count(void)
+u64 gv100_get_runcontrol_whitelist_ranges_count(void)
 {
         return gv100_runcontrol_whitelist_ranges_count;
 }
@@ -5696,7 +5696,7 @@ const u32 *gv100_get_qctl_whitelist(void)
         return gv100_qctl_whitelist;
 }
 
-int gv100_get_qctl_whitelist_count(void)
+u64 gv100_get_qctl_whitelist_count(void)
 {
         return gv100_qctl_whitelist_count;
 }
@@ -5706,7 +5706,7 @@ const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void)
         return gv100_qctl_whitelist_ranges;
 }
 
-int gv100_get_qctl_whitelist_ranges_count(void)
+u64 gv100_get_qctl_whitelist_ranges_count(void)
 {
         return gv100_qctl_whitelist_ranges_count;
 }
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.h b/drivers/gpu/nvgpu/gv100/regops_gv100.h
index 06e5b8e1..4abfeaac 100644
--- a/drivers/gpu/nvgpu/gv100/regops_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/regops_gv100.h
@@ -2,7 +2,7 @@
  *
  * Tegra GV100 GPU Driver Register Ops
  *
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,17 +26,17 @@
 #define __REGOPS_GV100_H_
 
 const struct regop_offset_range *gv100_get_global_whitelist_ranges(void);
-int gv100_get_global_whitelist_ranges_count(void);
+u64 gv100_get_global_whitelist_ranges_count(void);
 const struct regop_offset_range *gv100_get_context_whitelist_ranges(void);
-int gv100_get_context_whitelist_ranges_count(void);
+u64 gv100_get_context_whitelist_ranges_count(void);
 const u32 *gv100_get_runcontrol_whitelist(void);
-int gv100_get_runcontrol_whitelist_count(void);
+u64 gv100_get_runcontrol_whitelist_count(void);
 const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void);
-int gv100_get_runcontrol_whitelist_ranges_count(void);
+u64 gv100_get_runcontrol_whitelist_ranges_count(void);
 const u32 *gv100_get_qctl_whitelist(void);
-int gv100_get_qctl_whitelist_count(void);
+u64 gv100_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void);
-int gv100_get_qctl_whitelist_ranges_count(void);
+u64 gv100_get_qctl_whitelist_ranges_count(void);
 int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* __REGOPS_GV11B_H_ */
diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c
index f84b5066..768674fe 100644
--- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c
@@ -1441,7 +1441,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = {
 };
 
 
-static const u32 gv11b_global_whitelist_ranges_count =
+static const u64 gv11b_global_whitelist_ranges_count =
         ARRAY_SIZE(gv11b_global_whitelist_ranges);
 
 /* context */
@@ -1449,24 +1449,24 @@ static const u32 gv11b_global_whitelist_ranges_count =
 /* runcontrol */
 static const u32 gv11b_runcontrol_whitelist[] = {
 };
-static const u32 gv11b_runcontrol_whitelist_count =
+static const u64 gv11b_runcontrol_whitelist_count =
         ARRAY_SIZE(gv11b_runcontrol_whitelist);
 
 static const struct regop_offset_range gv11b_runcontrol_whitelist_ranges[] = {
 };
-static const u32 gv11b_runcontrol_whitelist_ranges_count =
+static const u64 gv11b_runcontrol_whitelist_ranges_count =
         ARRAY_SIZE(gv11b_runcontrol_whitelist_ranges);
 
 
 /* quad ctl */
 static const u32 gv11b_qctl_whitelist[] = {
 };
-static const u32 gv11b_qctl_whitelist_count =
+static const u64 gv11b_qctl_whitelist_count =
         ARRAY_SIZE(gv11b_qctl_whitelist);
 
 static const struct regop_offset_range gv11b_qctl_whitelist_ranges[] = {
 };
-static const u32 gv11b_qctl_whitelist_ranges_count =
+static const u64 gv11b_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gv11b_qctl_whitelist_ranges);
 
 const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void)
@@ -1474,7 +1474,7 @@ const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void)
         return gv11b_global_whitelist_ranges;
 }
 
-int gv11b_get_global_whitelist_ranges_count(void)
+u64 gv11b_get_global_whitelist_ranges_count(void)
 {
         return gv11b_global_whitelist_ranges_count;
 }
@@ -1484,7 +1484,7 @@ const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void)
         return gv11b_global_whitelist_ranges;
 }
 
-int gv11b_get_context_whitelist_ranges_count(void)
+u64 gv11b_get_context_whitelist_ranges_count(void)
 {
         return gv11b_global_whitelist_ranges_count;
 }
@@ -1494,7 +1494,7 @@ const u32 *gv11b_get_runcontrol_whitelist(void)
         return gv11b_runcontrol_whitelist;
 }
 
-int gv11b_get_runcontrol_whitelist_count(void)
+u64 gv11b_get_runcontrol_whitelist_count(void)
 {
         return gv11b_runcontrol_whitelist_count;
 }
@@ -1504,7 +1504,7 @@ const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void)
         return gv11b_runcontrol_whitelist_ranges;
 }
 
-int gv11b_get_runcontrol_whitelist_ranges_count(void)
+u64 gv11b_get_runcontrol_whitelist_ranges_count(void)
 {
         return gv11b_runcontrol_whitelist_ranges_count;
 }
@@ -1514,7 +1514,7 @@ const u32 *gv11b_get_qctl_whitelist(void)
         return gv11b_qctl_whitelist;
 }
 
-int gv11b_get_qctl_whitelist_count(void)
+u64 gv11b_get_qctl_whitelist_count(void)
 {
         return gv11b_qctl_whitelist_count;
 }
@@ -1524,7 +1524,7 @@ const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void)
         return gv11b_qctl_whitelist_ranges;
 }
 
-int gv11b_get_qctl_whitelist_ranges_count(void)
+u64 gv11b_get_qctl_whitelist_ranges_count(void)
 {
         return gv11b_qctl_whitelist_ranges_count;
 }
diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h
index 0ee2edfe..b605c0a6 100644
--- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h
@@ -2,7 +2,7 @@
  *
  * Tegra GV11B GPU Driver Register Ops
  *
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,17 +26,17 @@
 #define __REGOPS_GV11B_H_
 
 const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void);
-int gv11b_get_global_whitelist_ranges_count(void);
+u64 gv11b_get_global_whitelist_ranges_count(void);
 const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void);
-int gv11b_get_context_whitelist_ranges_count(void);
+u64 gv11b_get_context_whitelist_ranges_count(void);
 const u32 *gv11b_get_runcontrol_whitelist(void);
-int gv11b_get_runcontrol_whitelist_count(void);
+u64 gv11b_get_runcontrol_whitelist_count(void);
 const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void);
-int gv11b_get_runcontrol_whitelist_ranges_count(void);
+u64 gv11b_get_runcontrol_whitelist_ranges_count(void);
 const u32 *gv11b_get_qctl_whitelist(void);
-int gv11b_get_qctl_whitelist_count(void);
+u64 gv11b_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void);
-int gv11b_get_qctl_whitelist_ranges_count(void);
+u64 gv11b_get_qctl_whitelist_ranges_count(void);
 int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* __REGOPS_GV11B_H_ */