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author | Seema Khowala <seemaj@nvidia.com> | 2018-03-23 17:45:25 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-27 02:03:42 -0400 |
commit | 27908cf4a980cb56daa530641cf1817d4e3f9faa (patch) | |
tree | c9b3a4fc1a48e2297581f967b7ddcc6fc28a28dc /drivers/gpu/nvgpu | |
parent | a3a00f1d941f0bd180e0191a708a23579b1bede9 (diff) |
gpu: nvgpu: gv100: handle_tpc_sm_ecc_exception set to NULL
This is to fix *SM_ICACHE_ECC* priv errors for sm suspend
resume test. gv100 has significantly less ECC protected
SRAMs. gv11b ECC hals will not work for gv100.
Bug 1998067
Change-Id: I437a7981ed1832c2070185f3ad8f802c7454e8c9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1681270
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Sandarbh Jain <sanjain@nvidia.com>
Tested-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cfac8e0e..cb7bca3f 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -421,8 +421,6 @@ static const struct gpu_ops gv100_ops = { | |||
421 | .add_zbc_s = gr_gv11b_add_zbc_stencil, | 421 | .add_zbc_s = gr_gv11b_add_zbc_stencil, |
422 | .handle_gcc_exception = gr_gv11b_handle_gcc_exception, | 422 | .handle_gcc_exception = gr_gv11b_handle_gcc_exception, |
423 | .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, | 423 | .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, |
424 | .handle_tpc_sm_ecc_exception = | ||
425 | gr_gv11b_handle_tpc_sm_ecc_exception, | ||
426 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, | 424 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, |
427 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, | 425 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, |
428 | .handle_ssync_hww = gr_gv11b_handle_ssync_hww, | 426 | .handle_ssync_hww = gr_gv11b_handle_ssync_hww, |