diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-05-25 13:27:10 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:07 -0400 |
commit | 27694ca572c4d7698b107c6713f0f0604b41c186 (patch) | |
tree | 60dc8a1a8518797fd95f82d1e02892a984911667 /drivers/gpu/nvgpu | |
parent | 5c8f1619ce5ab1cf46484c8914fa29bcc208b9a0 (diff) |
gpu: nvgpu: Implement bus HAL for bar2 bind
Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL.
BAR2 bind HW API is in bus.
JIRA NVGPU-588
Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730896
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gp10b.c | 64 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gp10b.h | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 54 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 |
17 files changed, 116 insertions, 94 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 67a9c7f1..3cbe5b96 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -25,6 +25,7 @@ obj-$(CONFIG_GK20A) := nvgpu.o | |||
25 | 25 | ||
26 | nvgpu-y += common/bus/bus_gk20a.o \ | 26 | nvgpu-y += common/bus/bus_gk20a.o \ |
27 | common/bus/bus_gm20b.o \ | 27 | common/bus/bus_gm20b.o \ |
28 | common/bus/bus_gp10b.o \ | ||
28 | common/ptimer/ptimer.o \ | 29 | common/ptimer/ptimer.o \ |
29 | common/ptimer/ptimer_gk20a.o | 30 | common/ptimer/ptimer_gk20a.o |
30 | 31 | ||
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gp10b.c b/drivers/gpu/nvgpu/common/bus/bus_gp10b.c new file mode 100644 index 00000000..01e81069 --- /dev/null +++ b/drivers/gpu/nvgpu/common/bus/bus_gp10b.c | |||
@@ -0,0 +1,64 @@ | |||
1 | /* | ||
2 | * GM20B MMU | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/timers.h> | ||
26 | #include <nvgpu/mm.h> | ||
27 | |||
28 | #include "bus_gp10b.h" | ||
29 | #include "gk20a/gk20a.h" | ||
30 | |||
31 | #include <nvgpu/hw/gp10b/hw_bus_gp10b.h> | ||
32 | |||
33 | int gp10b_bus_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst) | ||
34 | { | ||
35 | struct nvgpu_timeout timeout; | ||
36 | int err = 0; | ||
37 | u64 iova = nvgpu_inst_block_addr(g, bar2_inst); | ||
38 | u32 ptr_v = (u32)(iova >> bus_bar2_block_ptr_shift_v()); | ||
39 | |||
40 | nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", ptr_v); | ||
41 | |||
42 | gk20a_writel(g, bus_bar2_block_r(), | ||
43 | nvgpu_aperture_mask(g, bar2_inst, | ||
44 | bus_bar2_block_target_sys_mem_ncoh_f(), | ||
45 | bus_bar2_block_target_sys_mem_coh_f(), | ||
46 | bus_bar2_block_target_vid_mem_f()) | | ||
47 | bus_bar2_block_mode_virtual_f() | | ||
48 | bus_bar2_block_ptr_f(ptr_v)); | ||
49 | nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); | ||
50 | do { | ||
51 | u32 val = gk20a_readl(g, bus_bind_status_r()); | ||
52 | u32 pending = bus_bind_status_bar2_pending_v(val); | ||
53 | u32 outstanding = bus_bind_status_bar2_outstanding_v(val); | ||
54 | if (!pending && !outstanding) | ||
55 | break; | ||
56 | |||
57 | nvgpu_udelay(5); | ||
58 | } while (!nvgpu_timeout_expired(&timeout)); | ||
59 | |||
60 | if (nvgpu_timeout_peek_expired(&timeout)) | ||
61 | err = -EINVAL; | ||
62 | |||
63 | return err; | ||
64 | } | ||
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gp10b.h b/drivers/gpu/nvgpu/common/bus/bus_gp10b.h new file mode 100644 index 00000000..0a356f15 --- /dev/null +++ b/drivers/gpu/nvgpu/common/bus/bus_gp10b.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * GM20B BUS | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_GP10B_BUS | ||
26 | #define _NVGPU_GP10B_BUS | ||
27 | |||
28 | struct gk20a; | ||
29 | struct nvgpu_mem; | ||
30 | |||
31 | int gp10b_bus_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); | ||
32 | |||
33 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 08a1fc10..d8941cdf 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -895,7 +895,6 @@ struct gpu_ops { | |||
895 | int (*init_mm_setup_hw)(struct gk20a *g); | 895 | int (*init_mm_setup_hw)(struct gk20a *g); |
896 | bool (*is_bar1_supported)(struct gk20a *g); | 896 | bool (*is_bar1_supported)(struct gk20a *g); |
897 | int (*init_bar2_vm)(struct gk20a *g); | 897 | int (*init_bar2_vm)(struct gk20a *g); |
898 | int (*init_bar2_mm_hw_setup)(struct gk20a *g); | ||
899 | void (*remove_bar2_vm)(struct gk20a *g); | 898 | void (*remove_bar2_vm)(struct gk20a *g); |
900 | const struct gk20a_mmu_level * | 899 | const struct gk20a_mmu_level * |
901 | (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); | 900 | (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); |
@@ -1121,6 +1120,7 @@ struct gpu_ops { | |||
1121 | void (*init_hw)(struct gk20a *g); | 1120 | void (*init_hw)(struct gk20a *g); |
1122 | void (*isr)(struct gk20a *g); | 1121 | void (*isr)(struct gk20a *g); |
1123 | int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); | 1122 | int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); |
1123 | int (*bar2_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); | ||
1124 | u32 (*set_bar0_window)(struct gk20a *g, struct nvgpu_mem *mem, | 1124 | u32 (*set_bar0_window)(struct gk20a *g, struct nvgpu_mem *mem, |
1125 | struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, | 1125 | struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, |
1126 | u32 w); | 1126 | u32 w); |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 9429fe2e..40d9e5b1 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -50,7 +50,6 @@ | |||
50 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 50 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
51 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> | 51 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> |
52 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 52 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
53 | #include <nvgpu/hw/gk20a/hw_bus_gk20a.h> | ||
54 | #include <nvgpu/hw/gk20a/hw_flush_gk20a.h> | 53 | #include <nvgpu/hw/gk20a/hw_flush_gk20a.h> |
55 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> | 54 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> |
56 | 55 | ||
@@ -103,8 +102,8 @@ int gk20a_init_mm_setup_hw(struct gk20a *g) | |||
103 | if (g->ops.bus.bar1_bind) | 102 | if (g->ops.bus.bar1_bind) |
104 | g->ops.bus.bar1_bind(g, &mm->bar1.inst_block); | 103 | g->ops.bus.bar1_bind(g, &mm->bar1.inst_block); |
105 | 104 | ||
106 | if (g->ops.mm.init_bar2_mm_hw_setup) { | 105 | if (g->ops.bus.bar2_bind) { |
107 | err = g->ops.mm.init_bar2_mm_hw_setup(g); | 106 | err = g->ops.bus.bar2_bind(g, &mm->bar2.inst_block); |
108 | if (err) | 107 | if (err) |
109 | return err; | 108 | return err; |
110 | } | 109 | } |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index eec0f917..f35abac7 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include "common/clock_gating/gp106_gating_reglist.h" | 26 | #include "common/clock_gating/gp106_gating_reglist.h" |
27 | #include "common/ptimer/ptimer_gk20a.h" | 27 | #include "common/ptimer/ptimer_gk20a.h" |
28 | #include "common/bus/bus_gm20b.h" | 28 | #include "common/bus/bus_gm20b.h" |
29 | #include "common/bus/bus_gp10b.h" | ||
29 | 30 | ||
30 | #include "gk20a/gk20a.h" | 31 | #include "gk20a/gk20a.h" |
31 | #include "gk20a/fifo_gk20a.h" | 32 | #include "gk20a/fifo_gk20a.h" |
@@ -583,7 +584,6 @@ static const struct gpu_ops gp106_ops = { | |||
583 | .init_inst_block = gk20a_init_inst_block, | 584 | .init_inst_block = gk20a_init_inst_block, |
584 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | 585 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, |
585 | .init_bar2_vm = gp10b_init_bar2_vm, | 586 | .init_bar2_vm = gp10b_init_bar2_vm, |
586 | .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup, | ||
587 | .remove_bar2_vm = gp10b_remove_bar2_vm, | 587 | .remove_bar2_vm = gp10b_remove_bar2_vm, |
588 | .get_vidmem_size = gp106_mm_get_vidmem_size, | 588 | .get_vidmem_size = gp106_mm_get_vidmem_size, |
589 | .get_kind_invalid = gm20b_get_kind_invalid, | 589 | .get_kind_invalid = gm20b_get_kind_invalid, |
@@ -723,6 +723,7 @@ static const struct gpu_ops gp106_ops = { | |||
723 | .init_hw = gk20a_bus_init_hw, | 723 | .init_hw = gk20a_bus_init_hw, |
724 | .isr = gk20a_bus_isr, | 724 | .isr = gk20a_bus_isr, |
725 | .bar1_bind = gm20b_bus_bar1_bind, | 725 | .bar1_bind = gm20b_bus_bar1_bind, |
726 | .bar2_bind = gp10b_bus_bar2_bind, | ||
726 | .set_bar0_window = gk20a_bus_set_bar0_window, | 727 | .set_bar0_window = gk20a_bus_set_bar0_window, |
727 | }, | 728 | }, |
728 | .ptimer = { | 729 | .ptimer = { |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 934ddb9a..8cd2a582 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include "common/clock_gating/gp10b_gating_reglist.h" | 26 | #include "common/clock_gating/gp10b_gating_reglist.h" |
27 | #include "common/ptimer/ptimer_gk20a.h" | 27 | #include "common/ptimer/ptimer_gk20a.h" |
28 | #include "common/bus/bus_gm20b.h" | 28 | #include "common/bus/bus_gm20b.h" |
29 | #include "common/bus/bus_gp10b.h" | ||
29 | 30 | ||
30 | #include "gk20a/gk20a.h" | 31 | #include "gk20a/gk20a.h" |
31 | #include "gk20a/fifo_gk20a.h" | 32 | #include "gk20a/fifo_gk20a.h" |
@@ -554,7 +555,6 @@ static const struct gpu_ops gp10b_ops = { | |||
554 | .init_inst_block = gk20a_init_inst_block, | 555 | .init_inst_block = gk20a_init_inst_block, |
555 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | 556 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, |
556 | .init_bar2_vm = gp10b_init_bar2_vm, | 557 | .init_bar2_vm = gp10b_init_bar2_vm, |
557 | .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup, | ||
558 | .remove_bar2_vm = gp10b_remove_bar2_vm, | 558 | .remove_bar2_vm = gp10b_remove_bar2_vm, |
559 | .get_kind_invalid = gm20b_get_kind_invalid, | 559 | .get_kind_invalid = gm20b_get_kind_invalid, |
560 | .get_kind_pitch = gm20b_get_kind_pitch, | 560 | .get_kind_pitch = gm20b_get_kind_pitch, |
@@ -653,6 +653,7 @@ static const struct gpu_ops gp10b_ops = { | |||
653 | .init_hw = gk20a_bus_init_hw, | 653 | .init_hw = gk20a_bus_init_hw, |
654 | .isr = gk20a_bus_isr, | 654 | .isr = gk20a_bus_isr, |
655 | .bar1_bind = gm20b_bus_bar1_bind, | 655 | .bar1_bind = gm20b_bus_bar1_bind, |
656 | .bar2_bind = gp10b_bus_bar2_bind, | ||
656 | .set_bar0_window = gk20a_bus_set_bar0_window, | 657 | .set_bar0_window = gk20a_bus_set_bar0_window, |
657 | }, | 658 | }, |
658 | .ptimer = { | 659 | .ptimer = { |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index acd42dd8..50c96f36 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -34,7 +34,6 @@ | |||
34 | 34 | ||
35 | #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> | 35 | #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> |
36 | #include <nvgpu/hw/gp10b/hw_ram_gp10b.h> | 36 | #include <nvgpu/hw/gp10b/hw_ram_gp10b.h> |
37 | #include <nvgpu/hw/gp10b/hw_bus_gp10b.h> | ||
38 | #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h> | 37 | #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h> |
39 | 38 | ||
40 | u32 gp10b_mm_get_default_big_page_size(void) | 39 | u32 gp10b_mm_get_default_big_page_size(void) |
@@ -62,8 +61,8 @@ int gp10b_init_mm_setup_hw(struct gk20a *g) | |||
62 | 61 | ||
63 | g->ops.bus.bar1_bind(g, inst_block); | 62 | g->ops.bus.bar1_bind(g, inst_block); |
64 | 63 | ||
65 | if (g->ops.mm.init_bar2_mm_hw_setup) { | 64 | if (g->ops.bus.bar2_bind) { |
66 | err = g->ops.mm.init_bar2_mm_hw_setup(g); | 65 | err = g->ops.bus.bar2_bind(g, &g->mm.bar2.inst_block); |
67 | if (err) | 66 | if (err) |
68 | return err; | 67 | return err; |
69 | } | 68 | } |
@@ -109,29 +108,6 @@ clean_up_va: | |||
109 | return err; | 108 | return err; |
110 | } | 109 | } |
111 | 110 | ||
112 | int gp10b_init_bar2_mm_hw_setup(struct gk20a *g) | ||
113 | { | ||
114 | struct mm_gk20a *mm = &g->mm; | ||
115 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; | ||
116 | u64 inst_pa = nvgpu_inst_block_addr(g, inst_block); | ||
117 | |||
118 | nvgpu_log_fn(g, " "); | ||
119 | |||
120 | inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); | ||
121 | nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", (u32)inst_pa); | ||
122 | |||
123 | gk20a_writel(g, bus_bar2_block_r(), | ||
124 | nvgpu_aperture_mask(g, inst_block, | ||
125 | bus_bar2_block_target_sys_mem_ncoh_f(), | ||
126 | bus_bar2_block_target_sys_mem_coh_f(), | ||
127 | bus_bar2_block_target_vid_mem_f()) | | ||
128 | bus_bar2_block_mode_virtual_f() | | ||
129 | bus_bar2_block_ptr_f(inst_pa)); | ||
130 | |||
131 | nvgpu_log_fn(g, "done"); | ||
132 | return 0; | ||
133 | } | ||
134 | |||
135 | static void update_gmmu_pde3_locked(struct vm_gk20a *vm, | 111 | static void update_gmmu_pde3_locked(struct vm_gk20a *vm, |
136 | const struct gk20a_mmu_level *l, | 112 | const struct gk20a_mmu_level *l, |
137 | struct nvgpu_gmmu_pd *pd, | 113 | struct nvgpu_gmmu_pd *pd, |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index 5522d02e..4f37aae6 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h | |||
@@ -32,7 +32,6 @@ u32 gp10b_mm_get_default_big_page_size(void); | |||
32 | u32 gp10b_mm_get_iommu_bit(struct gk20a *g); | 32 | u32 gp10b_mm_get_iommu_bit(struct gk20a *g); |
33 | int gp10b_init_mm_setup_hw(struct gk20a *g); | 33 | int gp10b_init_mm_setup_hw(struct gk20a *g); |
34 | int gp10b_init_bar2_vm(struct gk20a *g); | 34 | int gp10b_init_bar2_vm(struct gk20a *g); |
35 | int gp10b_init_bar2_mm_hw_setup(struct gk20a *g); | ||
36 | const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, | 35 | const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, |
37 | u32 big_page_size); | 36 | u32 big_page_size); |
38 | void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | 37 | void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, |
diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c index 3f089545..7a714441 100644 --- a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c | |||
@@ -30,7 +30,6 @@ | |||
30 | 30 | ||
31 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> | 31 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> |
32 | #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> | 32 | #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> |
33 | #include <nvgpu/hw/gp10b/hw_bus_gp10b.h> | ||
34 | #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h> | 33 | #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h> |
35 | 34 | ||
36 | int gp10b_replayable_pagefault_buffer_init(struct gk20a *g) | 35 | int gp10b_replayable_pagefault_buffer_init(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index dd3a5398..13e0c1a3 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -23,6 +23,7 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include "common/bus/bus_gk20a.h" | 25 | #include "common/bus/bus_gk20a.h" |
26 | #include "common/bus/bus_gp10b.h" | ||
26 | #include "common/clock_gating/gv100_gating_reglist.h" | 27 | #include "common/clock_gating/gv100_gating_reglist.h" |
27 | #include "common/ptimer/ptimer_gk20a.h" | 28 | #include "common/ptimer/ptimer_gk20a.h" |
28 | 29 | ||
@@ -653,7 +654,6 @@ static const struct gpu_ops gv100_ops = { | |||
653 | .get_kind_invalid = gm20b_get_kind_invalid, | 654 | .get_kind_invalid = gm20b_get_kind_invalid, |
654 | .get_kind_pitch = gm20b_get_kind_pitch, | 655 | .get_kind_pitch = gm20b_get_kind_pitch, |
655 | .init_bar2_vm = gp10b_init_bar2_vm, | 656 | .init_bar2_vm = gp10b_init_bar2_vm, |
656 | .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, | ||
657 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, | 657 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, |
658 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, | 658 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, |
659 | .get_flush_retries = gv100_mm_get_flush_retries, | 659 | .get_flush_retries = gv100_mm_get_flush_retries, |
@@ -792,6 +792,7 @@ static const struct gpu_ops gv100_ops = { | |||
792 | .init_hw = gk20a_bus_init_hw, | 792 | .init_hw = gk20a_bus_init_hw, |
793 | .isr = gk20a_bus_isr, | 793 | .isr = gk20a_bus_isr, |
794 | .bar1_bind = NULL, | 794 | .bar1_bind = NULL, |
795 | .bar2_bind = gp10b_bus_bar2_bind, | ||
795 | .set_bar0_window = gk20a_bus_set_bar0_window, | 796 | .set_bar0_window = gk20a_bus_set_bar0_window, |
796 | }, | 797 | }, |
797 | .ptimer = { | 798 | .ptimer = { |
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index bba47471..9fd6c857 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c | |||
@@ -1229,7 +1229,7 @@ static void gv11b_fb_handle_bar2_fault(struct gk20a *g, | |||
1229 | } | 1229 | } |
1230 | gv11b_ce_mthd_buffer_fault_in_bar2_fault(g); | 1230 | gv11b_ce_mthd_buffer_fault_in_bar2_fault(g); |
1231 | 1231 | ||
1232 | g->ops.mm.init_bar2_mm_hw_setup(g); | 1232 | g->ops.bus.bar2_bind(g, &g->mm.bar2.inst_block); |
1233 | 1233 | ||
1234 | if (mmfault->refch) { | 1234 | if (mmfault->refch) { |
1235 | gk20a_channel_put(mmfault->refch); | 1235 | gk20a_channel_put(mmfault->refch); |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 7b552723..58912a30 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -23,6 +23,7 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include "common/bus/bus_gk20a.h" | 25 | #include "common/bus/bus_gk20a.h" |
26 | #include "common/bus/bus_gp10b.h" | ||
26 | #include "common/clock_gating/gv11b_gating_reglist.h" | 27 | #include "common/clock_gating/gv11b_gating_reglist.h" |
27 | #include "common/ptimer/ptimer_gk20a.h" | 28 | #include "common/ptimer/ptimer_gk20a.h" |
28 | 29 | ||
@@ -621,7 +622,6 @@ static const struct gpu_ops gv11b_ops = { | |||
621 | .get_kind_invalid = gm20b_get_kind_invalid, | 622 | .get_kind_invalid = gm20b_get_kind_invalid, |
622 | .get_kind_pitch = gm20b_get_kind_pitch, | 623 | .get_kind_pitch = gm20b_get_kind_pitch, |
623 | .init_bar2_vm = gp10b_init_bar2_vm, | 624 | .init_bar2_vm = gp10b_init_bar2_vm, |
624 | .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, | ||
625 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, | 625 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, |
626 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, | 626 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, |
627 | }, | 627 | }, |
@@ -724,6 +724,7 @@ static const struct gpu_ops gv11b_ops = { | |||
724 | .init_hw = gk20a_bus_init_hw, | 724 | .init_hw = gk20a_bus_init_hw, |
725 | .isr = gk20a_bus_isr, | 725 | .isr = gk20a_bus_isr, |
726 | .bar1_bind = NULL, | 726 | .bar1_bind = NULL, |
727 | .bar2_bind = gp10b_bus_bar2_bind, | ||
727 | .set_bar0_window = gk20a_bus_set_bar0_window, | 728 | .set_bar0_window = gk20a_bus_set_bar0_window, |
728 | }, | 729 | }, |
729 | .ptimer = { | 730 | .ptimer = { |
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 357b15d7..6c38365c 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c | |||
@@ -40,7 +40,6 @@ | |||
40 | 40 | ||
41 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> | 41 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> |
42 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> | 42 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> |
43 | #include <nvgpu/hw/gv11b/hw_bus_gv11b.h> | ||
44 | 43 | ||
45 | #define NVGPU_L3_ALLOC_BIT BIT(36) | 44 | #define NVGPU_L3_ALLOC_BIT BIT(36) |
46 | 45 | ||
@@ -236,7 +235,7 @@ int gv11b_init_mm_setup_hw(struct gk20a *g) | |||
236 | g->ops.fb.set_mmu_page_size(g); | 235 | g->ops.fb.set_mmu_page_size(g); |
237 | g->ops.fb.init_hw(g); | 236 | g->ops.fb.init_hw(g); |
238 | 237 | ||
239 | err = g->ops.mm.init_bar2_mm_hw_setup(g); | 238 | err = g->ops.bus.bar2_bind(g, &g->mm.bar2.inst_block); |
240 | if (err) | 239 | if (err) |
241 | return err; | 240 | return err; |
242 | 241 | ||
@@ -274,54 +273,3 @@ u64 gv11b_gpu_phys_addr(struct gk20a *g, | |||
274 | 273 | ||
275 | return phys; | 274 | return phys; |
276 | } | 275 | } |
277 | |||
278 | int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) | ||
279 | { | ||
280 | struct mm_gk20a *mm = &g->mm; | ||
281 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; | ||
282 | u64 inst_pa = nvgpu_inst_block_addr(g, inst_block); | ||
283 | u32 reg_val; | ||
284 | struct nvgpu_timeout timeout; | ||
285 | u32 delay = GR_IDLE_CHECK_DEFAULT; | ||
286 | |||
287 | nvgpu_log_fn(g, " "); | ||
288 | |||
289 | g->ops.fb.set_mmu_page_size(g); | ||
290 | |||
291 | inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); | ||
292 | nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", (u32)inst_pa); | ||
293 | |||
294 | gk20a_writel(g, bus_bar2_block_r(), | ||
295 | nvgpu_aperture_mask(g, inst_block, | ||
296 | bus_bar2_block_target_sys_mem_ncoh_f(), | ||
297 | bus_bar2_block_target_sys_mem_coh_f(), | ||
298 | bus_bar2_block_target_vid_mem_f()) | | ||
299 | bus_bar2_block_mode_virtual_f() | | ||
300 | bus_bar2_block_ptr_f(inst_pa)); | ||
301 | |||
302 | /* This is needed as BAR1 support is removed and there is no way | ||
303 | * to know if gpu successfully accessed memory. | ||
304 | * To avoid deadlocks and non-deterministic virtual address translation | ||
305 | * behavior, after writing BAR2_BLOCK to bind BAR2 to a virtual address | ||
306 | * space, SW must ensure that the bind has completed prior to issuing | ||
307 | * any further BAR2 requests by polling for both | ||
308 | * BUS_BIND_STATUS_BAR2_PENDING to return to EMPTY and | ||
309 | * BUS_BIND_STATUS_BAR2_OUTSTANDING to return to FALSE | ||
310 | */ | ||
311 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), | ||
312 | NVGPU_TIMER_CPU_TIMER); | ||
313 | nvgpu_log_info(g, "check bar2 bind status"); | ||
314 | do { | ||
315 | reg_val = gk20a_readl(g, bus_bind_status_r()); | ||
316 | |||
317 | if (!((reg_val & bus_bind_status_bar2_pending_busy_f()) || | ||
318 | (reg_val & bus_bind_status_bar2_outstanding_true_f()))) | ||
319 | return 0; | ||
320 | |||
321 | nvgpu_usleep_range(delay, delay * 2); | ||
322 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | ||
323 | } while (!nvgpu_timeout_expired_msg(&timeout, "bar2 bind timedout")); | ||
324 | |||
325 | nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); | ||
326 | return -EBUSY; | ||
327 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h index 2b3ebf4e..f5f89d94 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h | |||
@@ -34,7 +34,6 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, | |||
34 | bool gv11b_mm_mmu_fault_pending(struct gk20a *g); | 34 | bool gv11b_mm_mmu_fault_pending(struct gk20a *g); |
35 | void gv11b_mm_remove_bar2_vm(struct gk20a *g); | 35 | void gv11b_mm_remove_bar2_vm(struct gk20a *g); |
36 | int gv11b_init_mm_setup_hw(struct gk20a *g); | 36 | int gv11b_init_mm_setup_hw(struct gk20a *g); |
37 | int gv11b_init_bar2_mm_hw_setup(struct gk20a *g); | ||
38 | void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate); | 37 | void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate); |
39 | u64 gv11b_gpu_phys_addr(struct gk20a *g, | 38 | u64 gv11b_gpu_phys_addr(struct gk20a *g, |
40 | struct nvgpu_gmmu_attrs *attrs, u64 phys); | 39 | struct nvgpu_gmmu_attrs *attrs, u64 phys); |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index c4ffe126..8c2b613f 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -427,7 +427,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
427 | .init_inst_block = gk20a_init_inst_block, | 427 | .init_inst_block = gk20a_init_inst_block, |
428 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | 428 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, |
429 | .init_bar2_vm = gp10b_init_bar2_vm, | 429 | .init_bar2_vm = gp10b_init_bar2_vm, |
430 | .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup, | ||
431 | .remove_bar2_vm = gp10b_remove_bar2_vm, | 430 | .remove_bar2_vm = gp10b_remove_bar2_vm, |
432 | .get_kind_invalid = gm20b_get_kind_invalid, | 431 | .get_kind_invalid = gm20b_get_kind_invalid, |
433 | .get_kind_pitch = gm20b_get_kind_pitch, | 432 | .get_kind_pitch = gm20b_get_kind_pitch, |
@@ -524,7 +523,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
524 | .bus = { | 523 | .bus = { |
525 | .init_hw = gk20a_bus_init_hw, | 524 | .init_hw = gk20a_bus_init_hw, |
526 | .isr = gk20a_bus_isr, | 525 | .isr = gk20a_bus_isr, |
527 | .bar1_bind = gm20b_bus_bar1_bind, | 526 | .bar1_bind = NULL, |
527 | .bar2_bind = NULL, | ||
528 | .set_bar0_window = gk20a_bus_set_bar0_window, | 528 | .set_bar0_window = gk20a_bus_set_bar0_window, |
529 | }, | 529 | }, |
530 | .ptimer = { | 530 | .ptimer = { |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index d6b305d4..450c9c87 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -476,7 +476,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
476 | .get_kind_invalid = gm20b_get_kind_invalid, | 476 | .get_kind_invalid = gm20b_get_kind_invalid, |
477 | .get_kind_pitch = gm20b_get_kind_pitch, | 477 | .get_kind_pitch = gm20b_get_kind_pitch, |
478 | .init_bar2_vm = gp10b_init_bar2_vm, | 478 | .init_bar2_vm = gp10b_init_bar2_vm, |
479 | .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, | ||
480 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, | 479 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, |
481 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, | 480 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, |
482 | }, | 481 | }, |
@@ -575,6 +574,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
575 | .init_hw = gk20a_bus_init_hw, | 574 | .init_hw = gk20a_bus_init_hw, |
576 | .isr = gk20a_bus_isr, | 575 | .isr = gk20a_bus_isr, |
577 | .bar1_bind = NULL, | 576 | .bar1_bind = NULL, |
577 | .bar2_bind = NULL, | ||
578 | .set_bar0_window = gk20a_bus_set_bar0_window, | 578 | .set_bar0_window = gk20a_bus_set_bar0_window, |
579 | }, | 579 | }, |
580 | .ptimer = { | 580 | .ptimer = { |