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authorseshendra Gadagottu <sgadagottu@nvidia.com>2017-09-20 15:20:56 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-09-25 19:57:13 -0400
commit1c0ea341cccf715eb117a0c22e83e25a64a38de7 (patch)
treef3d8acf05cb069f6acbf1590dc58578e02842305 /drivers/gpu/nvgpu
parent82ef5f7b3b51bff51b18f525ee14033a4b6befd4 (diff)
gpu: nvgpu: cpu access for ctxheader
Before updating ctxheader in gr_gk20a_ctx_patch_smpc() add cpu access with nvgpu_mem_begin. After updating ctxheader, close cpu access with nvgpu_mem_end. Reviewed usage of ctxheader in other places and its cpu access is taken care correctly. Bug 200333285 Change-Id: I88ab0b040f95240673a4be55bcfe880a1440655b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1564764 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 263d8bac..faecb815 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6586,12 +6586,22 @@ static int gr_gk20a_ctx_patch_smpc(struct gk20a *g,
6586 ctxsw_prog_main_image_patch_count_o(), 6586 ctxsw_prog_main_image_patch_count_o(),
6587 ch_ctx->patch_ctx.data_count); 6587 ch_ctx->patch_ctx.data_count);
6588 if (ctxheader->gpu_va) { 6588 if (ctxheader->gpu_va) {
6589 /*
6590 * Main context can be gr_ctx or pm_ctx.
6591 * CPU access for relevant ctx is taken
6592 * care of in the calling function
6593 * __gr_gk20a_exec_ctx_ops. Need to take
6594 * care of cpu access to ctxheader here.
6595 */
6596 if (nvgpu_mem_begin(g, ctxheader))
6597 return -ENOMEM;
6589 nvgpu_mem_wr(g, ctxheader, 6598 nvgpu_mem_wr(g, ctxheader,
6590 ctxsw_prog_main_image_patch_adr_lo_o(), 6599 ctxsw_prog_main_image_patch_adr_lo_o(),
6591 vaddr_lo); 6600 vaddr_lo);
6592 nvgpu_mem_wr(g, ctxheader, 6601 nvgpu_mem_wr(g, ctxheader,
6593 ctxsw_prog_main_image_patch_adr_hi_o(), 6602 ctxsw_prog_main_image_patch_adr_hi_o(),
6594 vaddr_hi); 6603 vaddr_hi);
6604 nvgpu_mem_end(g, ctxheader);
6595 } else { 6605 } else {
6596 nvgpu_mem_wr(g, mem, 6606 nvgpu_mem_wr(g, mem,
6597 ctxsw_prog_main_image_patch_adr_lo_o(), 6607 ctxsw_prog_main_image_patch_adr_lo_o(),