gpu: nvgpu: add exception registers to dump

Add below exception registers to GR dump :
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN

Bug 200078514

Change-Id: Ib0ec34f7bf5a136928c53cf8398b4929fb4639c5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/712480
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 files changed, 72 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index f632245e..b0fd3c0c 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -7437,6 +7437,18 @@ static int gr_gk20a_dump_gr_status_regs(struct gk20a *g,
                 gk20a_readl(g, gr_pri_bes_zrop_status_r()));
         gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS2 : 0x%x\n",
                 gk20a_readl(g, gr_pri_bes_zrop_status2_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION: 0x%x\n",
+                gk20a_readl(g, gr_pri_be0_becs_be_exception_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN: 0x%x\n",
+                gk20a_readl(g, gr_pri_be0_becs_be_exception_en_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION: 0x%x\n",
+                gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN: 0x%x\n",
+                gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_en_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION: 0x%x\n",
+                gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n",
+                gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r()));
         return 0;
 }
 
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
index d3345a51..ff698a51 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
@@ -298,6 +298,30 @@ static inline u32 gr_engine_status_value_busy_f(void)
 {
         return 0x1;
 }
+static inline u32 gr_pri_be0_becs_be_exception_r(void)
+{
+        return 0x00410204;
+}
+static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
+{
+        return 0x00410208;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
+{
+        return 0x00502c94;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450c;
+}
 static inline u32 gr_activity_0_r(void)
 {
         return 0x00400380;
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 79e46421..da1c1ab0 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -934,6 +934,18 @@ static int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
                 gk20a_readl(g, gr_pri_bes_zrop_status_r()));
         gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS2 : 0x%x\n",
                 gk20a_readl(g, gr_pri_bes_zrop_status2_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION: 0x%x\n",
+                gk20a_readl(g, gr_pri_be0_becs_be_exception_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN: 0x%x\n",
+                gk20a_readl(g, gr_pri_be0_becs_be_exception_en_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION: 0x%x\n",
+                gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN: 0x%x\n",
+                gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_en_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION: 0x%x\n",
+                gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n",
+                gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r()));
         return 0;
 }
 
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
index 9c33321f..543c7773 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
@@ -286,6 +286,30 @@ static inline u32 gr_engine_status_value_busy_f(void)
 {
         return 0x1;
 }
+static inline u32 gr_pri_be0_becs_be_exception_r(void)
+{
+        return 0x00410204;
+}
+static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
+{
+        return 0x00410208;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
+{
+        return 0x00502c94;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450c;
+}
 static inline u32 gr_activity_0_r(void)
 {
         return 0x00400380;