diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-02-16 19:55:08 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-12 18:33:50 -0400 |
commit | 1b4849cda595b5b4e55fdb51e7ecd6c09e1a5fa4 (patch) | |
tree | ffd65ae5794ddb39c8bd320b4b7fab2bbc35fd74 /drivers/gpu/nvgpu | |
parent | 60d0ba2d37b4f2b67ecf0be4d6566af5a289ccb9 (diff) |
gpu: nvgpu: gv11b: init pbdma_intr_0 handler
Add handling for below two interrupts on top of legacy ones. When pending,
PBDMA is stalled and s/w is expected to execute teardown.
clear_faulted_error: host is asked to clear fault status when no fault has been asserted.
eng_reset: An engine was reset while the PBDMA unit was processing a
channel from a runlist which serves the engine.
JIRA GPUT19X-47
Change-Id: I776e5799a73a1b63c394048fa61b597e621cf544
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1306558
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index d3411d32..e4dd6a63 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1375,6 +1375,33 @@ static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) | |||
1375 | return ret; | 1375 | return ret; |
1376 | } | 1376 | } |
1377 | 1377 | ||
1378 | static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, | ||
1379 | u32 pbdma_id, u32 pbdma_intr_0, | ||
1380 | u32 *handled, u32 *error_notifier) | ||
1381 | { | ||
1382 | unsigned int rc_type = RC_TYPE_NO_RC; | ||
1383 | |||
1384 | rc_type = gk20a_fifo_handle_pbdma_intr_0(g, pbdma_id, | ||
1385 | pbdma_intr_0, handled, error_notifier); | ||
1386 | |||
1387 | if (pbdma_intr_0 & pbdma_intr_0_clear_faulted_error_pending_f()) { | ||
1388 | gk20a_dbg(gpu_dbg_intr, "clear faulted error on pbdma id %d", | ||
1389 | pbdma_id); | ||
1390 | gk20a_fifo_reset_pbdma_method(g, pbdma_id, 0); | ||
1391 | *handled |= pbdma_intr_0_clear_faulted_error_pending_f(); | ||
1392 | rc_type = RC_TYPE_PBDMA_FAULT; | ||
1393 | } | ||
1394 | |||
1395 | if (pbdma_intr_0 & pbdma_intr_0_eng_reset_pending_f()) { | ||
1396 | gk20a_dbg(gpu_dbg_intr, "eng reset intr on pbdma id %d", | ||
1397 | pbdma_id); | ||
1398 | *handled |= pbdma_intr_0_eng_reset_pending_f(); | ||
1399 | rc_type = RC_TYPE_PBDMA_FAULT; | ||
1400 | } | ||
1401 | |||
1402 | return rc_type; | ||
1403 | } | ||
1404 | |||
1378 | void gv11b_init_fifo(struct gpu_ops *gops) | 1405 | void gv11b_init_fifo(struct gpu_ops *gops) |
1379 | { | 1406 | { |
1380 | gp10b_init_fifo(gops); | 1407 | gp10b_init_fifo(gops); |
@@ -1407,4 +1434,6 @@ void gv11b_init_fifo(struct gpu_ops *gops) | |||
1407 | gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; | 1434 | gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; |
1408 | gops->fifo.handle_sched_error = gv11b_fifo_handle_sched_error; | 1435 | gops->fifo.handle_sched_error = gv11b_fifo_handle_sched_error; |
1409 | gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; | 1436 | gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; |
1437 | gops->fifo.handle_pbdma_intr_0 = | ||
1438 | gv11b_fifo_handle_pbdma_intr_0; | ||
1410 | } | 1439 | } |