diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-02-14 04:01:01 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-15 02:46:59 -0400 |
commit | d3f96dfa96a8aafe6f5035e2ed24425141e4202e (patch) | |
tree | 05eb958518d5e6d9f31d607d1a9cf2f6e39ce295 /drivers/gpu/nvgpu/volt | |
parent | e77ec1a98e6d65eac5b56999af17d51ffca6671f (diff) |
gpu: nvgpu: gv10x volt rail boardobj changes
- Created volt ops under pmu_ver to support volt_set_voltage,
volt_get_voltage & volt_send_load_cmd_to_pmu.
- Renamed volt load, set_voltage & get_voltage gp10x method names.
- Added new volt load, set_voltage & get_voltage methods for gv10x
using RPC & added code to handle ack in pmu_rpc_handler() along
with struct rail_list changes.
- Updated volt ops of gp106 & gv100 to point to respective methods.
- Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to
"struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail"
made changes to update members as needed.
- Added member volt_scale_exp_pwr_equ_idx to
"struct vbios_voltage_rail_table_1x_entry" to read
value from VBIOS table & update rail boardobj set interface.
- Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*"
- Define struct's volt load, set_voltage & get_voltage to execute
volt RPC.
Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1659728
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/volt')
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_pmu.c | 110 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_pmu.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_rail.c | 35 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_rail.h | 4 |
4 files changed, 155 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c index 915db9a7..4608918c 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/volt/volt_pmu.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -115,7 +115,7 @@ volt_pmu_rpc_execute: | |||
115 | return status; | 115 | return status; |
116 | } | 116 | } |
117 | 117 | ||
118 | u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g) | 118 | u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g) |
119 | { | 119 | { |
120 | struct nv_pmu_volt_rpc rpc_call = { 0 }; | 120 | struct nv_pmu_volt_rpc rpc_call = { 0 }; |
121 | u32 status = 0; | 121 | u32 status = 0; |
@@ -131,7 +131,23 @@ u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g) | |||
131 | return status; | 131 | return status; |
132 | } | 132 | } |
133 | 133 | ||
134 | static u32 volt_rail_get_voltage(struct gk20a *g, | 134 | u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g) |
135 | { | ||
136 | struct nvgpu_pmu *pmu = &g->pmu; | ||
137 | struct nv_pmu_rpc_struct_volt_load rpc; | ||
138 | u32 status = 0; | ||
139 | |||
140 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_load)); | ||
141 | PMU_RPC_EXECUTE(status, pmu, VOLT, LOAD, &rpc, 0); | ||
142 | if (status) { | ||
143 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
144 | status); | ||
145 | } | ||
146 | |||
147 | return status; | ||
148 | } | ||
149 | |||
150 | u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g, | ||
135 | u8 volt_domain, u32 *pvoltage_uv) | 151 | u8 volt_domain, u32 *pvoltage_uv) |
136 | { | 152 | { |
137 | struct nv_pmu_volt_rpc rpc_call = { 0 }; | 153 | struct nv_pmu_volt_rpc rpc_call = { 0 }; |
@@ -165,6 +181,37 @@ static u32 volt_rail_get_voltage(struct gk20a *g, | |||
165 | return status; | 181 | return status; |
166 | } | 182 | } |
167 | 183 | ||
184 | u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g, | ||
185 | u8 volt_domain, u32 *pvoltage_uv) | ||
186 | { | ||
187 | struct nvgpu_pmu *pmu = &g->pmu; | ||
188 | struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage rpc; | ||
189 | u32 status = 0; | ||
190 | u8 rail_idx; | ||
191 | |||
192 | rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain); | ||
193 | if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) || | ||
194 | (!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu.volt, rail_idx))) { | ||
195 | nvgpu_err(g, | ||
196 | "failed: volt_domain = %d, voltage rail table = %d.", | ||
197 | volt_domain, rail_idx); | ||
198 | return -EINVAL; | ||
199 | } | ||
200 | |||
201 | memset(&rpc, 0, | ||
202 | sizeof(struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage)); | ||
203 | rpc.rail_idx = rail_idx; | ||
204 | |||
205 | PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0); | ||
206 | if (status) { | ||
207 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
208 | status); | ||
209 | } | ||
210 | |||
211 | *pvoltage_uv = rpc.voltage_uv; | ||
212 | |||
213 | return status; | ||
214 | } | ||
168 | 215 | ||
169 | static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id, | 216 | static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id, |
170 | struct ctrl_perf_volt_rail_list *prail_list) | 217 | struct ctrl_perf_volt_rail_list *prail_list) |
@@ -217,9 +264,54 @@ exit: | |||
217 | return status; | 264 | return status; |
218 | } | 265 | } |
219 | 266 | ||
220 | u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv) | 267 | static u32 volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id, |
268 | struct ctrl_volt_volt_rail_list_v1 *prail_list) | ||
221 | { | 269 | { |
222 | u32 status = 0; | 270 | struct nvgpu_pmu *pmu = &g->pmu; |
271 | struct nv_pmu_rpc_struct_volt_volt_set_voltage rpc; | ||
272 | int status = 0; | ||
273 | |||
274 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_volt_set_voltage)); | ||
275 | rpc.client_id = 0x1; | ||
276 | rpc.rail_list = *prail_list; | ||
277 | |||
278 | PMU_RPC_EXECUTE(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0); | ||
279 | if (status) { | ||
280 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
281 | status); | ||
282 | } | ||
283 | |||
284 | return status; | ||
285 | } | ||
286 | |||
287 | u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv, | ||
288 | u32 sram_voltage_uv) | ||
289 | { | ||
290 | int status = 0; | ||
291 | struct ctrl_volt_volt_rail_list_v1 rail_list = { 0 }; | ||
292 | |||
293 | rail_list.num_rails = RAIL_COUNT; | ||
294 | rail_list.rails[0].rail_idx = | ||
295 | volt_rail_volt_domain_convert_to_idx(g, | ||
296 | CTRL_VOLT_DOMAIN_LOGIC); | ||
297 | rail_list.rails[0].voltage_uv = logic_voltage_uv; | ||
298 | rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv; | ||
299 | rail_list.rails[1].rail_idx = | ||
300 | volt_rail_volt_domain_convert_to_idx(g, | ||
301 | CTRL_VOLT_DOMAIN_SRAM); | ||
302 | rail_list.rails[1].voltage_uv = sram_voltage_uv; | ||
303 | rail_list.rails[1].voltage_min_noise_unaware_uv = sram_voltage_uv; | ||
304 | |||
305 | status = volt_set_voltage_gv10x_rpc(g, | ||
306 | CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list); | ||
307 | |||
308 | return status; | ||
309 | } | ||
310 | |||
311 | u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv, | ||
312 | u32 sram_voltage_uv) | ||
313 | { | ||
314 | int status = 0; | ||
223 | struct ctrl_perf_volt_rail_list rail_list = { 0 }; | 315 | struct ctrl_perf_volt_rail_list rail_list = { 0 }; |
224 | 316 | ||
225 | rail_list.num_rails = RAIL_COUNT; | 317 | rail_list.num_rails = RAIL_COUNT; |
@@ -234,12 +326,18 @@ u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv) | |||
234 | CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list); | 326 | CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list); |
235 | 327 | ||
236 | return status; | 328 | return status; |
329 | } | ||
237 | 330 | ||
331 | u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv) | ||
332 | { | ||
333 | return g->ops.pmu_ver.volt.volt_set_voltage(g, | ||
334 | logic_voltage_uv, sram_voltage_uv); | ||
238 | } | 335 | } |
239 | 336 | ||
240 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv) | 337 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv) |
241 | { | 338 | { |
242 | return volt_rail_get_voltage(g, volt_domain, voltage_uv); | 339 | return g->ops.pmu_ver.volt.volt_get_voltage(g, |
340 | volt_domain, voltage_uv); | ||
243 | } | 341 | } |
244 | 342 | ||
245 | static int volt_policy_set_noiseaware_vmin(struct gk20a *g, | 343 | static int volt_policy_set_noiseaware_vmin(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.h b/drivers/gpu/nvgpu/volt/volt_pmu.h index 55be9c45..fbdf7c1e 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.h +++ b/drivers/gpu/nvgpu/volt/volt_pmu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -29,4 +29,18 @@ u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, | |||
29 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv); | 29 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv); |
30 | int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv, | 30 | int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv, |
31 | u32 sram_voltage_uv); | 31 | u32 sram_voltage_uv); |
32 | |||
33 | u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv, | ||
34 | u32 sram_voltage_uv); | ||
35 | u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g, | ||
36 | u8 volt_domain, u32 *pvoltage_uv); | ||
37 | u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g); | ||
38 | |||
39 | u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv, | ||
40 | u32 sram_voltage_uv); | ||
41 | u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g, | ||
42 | u8 volt_domain, u32 *pvoltage_uv); | ||
43 | u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g); | ||
44 | |||
45 | |||
32 | #endif | 46 | #endif |
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c index f78fc315..3461653f 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/volt/volt_rail.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -34,8 +34,10 @@ u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain) | |||
34 | { | 34 | { |
35 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { | 35 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { |
36 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: | 36 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: |
37 | if (volt_domain == CTRL_BOARDOBJ_IDX_INVALID) | 37 | switch (volt_domain) { |
38 | case CTRL_VOLT_DOMAIN_LOGIC: | ||
38 | return 0; | 39 | return 0; |
40 | } | ||
39 | break; | 41 | break; |
40 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: | 42 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: |
41 | switch (volt_domain) { | 43 | switch (volt_domain) { |
@@ -63,6 +65,22 @@ u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail | |||
63 | status = -EINVAL; | 65 | status = -EINVAL; |
64 | goto exit; | 66 | goto exit; |
65 | } | 67 | } |
68 | } else if (operation_type == | ||
69 | CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN) { | ||
70 | if (pvolt_rail->volt_dev_idx_ipc_vmin == | ||
71 | CTRL_BOARDOBJ_IDX_INVALID) { | ||
72 | pvolt_rail->volt_dev_idx_ipc_vmin = volt_dev_idx; | ||
73 | /* | ||
74 | * Exit on purpose as we do not want to register | ||
75 | * IPC_VMIN device against the rail to avoid | ||
76 | * setting current voltage instead of | ||
77 | * IPC Vmin voltage. | ||
78 | */ | ||
79 | goto exit; | ||
80 | } else { | ||
81 | status = -EINVAL; | ||
82 | goto exit; | ||
83 | } | ||
66 | } else { | 84 | } else { |
67 | goto exit; | 85 | goto exit; |
68 | } | 86 | } |
@@ -136,6 +154,9 @@ static u32 volt_rail_init_pmudata_super(struct gk20a *g, | |||
136 | prail->volt_margin_limit_vfe_equ_idx; | 154 | prail->volt_margin_limit_vfe_equ_idx; |
137 | rail_pmu_data->pwr_equ_idx = prail->pwr_equ_idx; | 155 | rail_pmu_data->pwr_equ_idx = prail->pwr_equ_idx; |
138 | rail_pmu_data->volt_dev_idx_default = prail->volt_dev_idx_default; | 156 | rail_pmu_data->volt_dev_idx_default = prail->volt_dev_idx_default; |
157 | rail_pmu_data->volt_scale_exp_pwr_equ_idx = | ||
158 | prail->volt_scale_exp_pwr_equ_idx; | ||
159 | rail_pmu_data->volt_dev_idx_ipc_vmin = prail->volt_dev_idx_ipc_vmin; | ||
139 | 160 | ||
140 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { | 161 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { |
141 | rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + | 162 | rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + |
@@ -187,6 +208,8 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs) | |||
187 | ptemp_rail->vmin_limit_vfe_equ_idx; | 208 | ptemp_rail->vmin_limit_vfe_equ_idx; |
188 | board_obj_volt_rail_ptr->volt_margin_limit_vfe_equ_idx = | 209 | board_obj_volt_rail_ptr->volt_margin_limit_vfe_equ_idx = |
189 | ptemp_rail->volt_margin_limit_vfe_equ_idx; | 210 | ptemp_rail->volt_margin_limit_vfe_equ_idx; |
211 | board_obj_volt_rail_ptr->volt_scale_exp_pwr_equ_idx = | ||
212 | ptemp_rail->volt_scale_exp_pwr_equ_idx; | ||
190 | 213 | ||
191 | gk20a_dbg_info("Done"); | 214 | gk20a_dbg_info("Done"); |
192 | 215 | ||
@@ -285,6 +308,14 @@ static u32 volt_get_volt_rail_table(struct gk20a *g, | |||
285 | (u8)entry.ov_limit_vfe_equ_idx; | 308 | (u8)entry.ov_limit_vfe_equ_idx; |
286 | 309 | ||
287 | if (header.table_entry_size >= | 310 | if (header.table_entry_size >= |
311 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C) | ||
312 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | ||
313 | (u8)entry.volt_scale_exp_pwr_equ_idx; | ||
314 | else | ||
315 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | ||
316 | CTRL_BOARDOBJ_IDX_INVALID; | ||
317 | |||
318 | if (header.table_entry_size >= | ||
288 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) | 319 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) |
289 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = | 320 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = |
290 | (u8)entry.volt_margin_limit_vfe_equ_idx; | 321 | (u8)entry.volt_margin_limit_vfe_equ_idx; |
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.h b/drivers/gpu/nvgpu/volt/volt_rail.h index 9a3fcda0..be3cbb72 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.h +++ b/drivers/gpu/nvgpu/volt/volt_rail.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -51,7 +51,9 @@ struct voltage_rail { | |||
51 | u8 alt_rel_limit_vfe_equ_idx; | 51 | u8 alt_rel_limit_vfe_equ_idx; |
52 | u8 ov_limit_vfe_equ_idx; | 52 | u8 ov_limit_vfe_equ_idx; |
53 | u8 pwr_equ_idx; | 53 | u8 pwr_equ_idx; |
54 | u8 volt_scale_exp_pwr_equ_idx; | ||
54 | u8 volt_dev_idx_default; | 55 | u8 volt_dev_idx_default; |
56 | u8 volt_dev_idx_ipc_vmin; | ||
55 | u8 boot_volt_vfe_equ_idx; | 57 | u8 boot_volt_vfe_equ_idx; |
56 | u8 vmin_limit_vfe_equ_idx; | 58 | u8 vmin_limit_vfe_equ_idx; |
57 | u8 volt_margin_limit_vfe_equ_idx; | 59 | u8 volt_margin_limit_vfe_equ_idx; |