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authorMahantesh Kumbar <mkumbar@nvidia.com>2016-09-27 05:24:50 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:50 -0500
commitaf637c81fe6360dbe81373b6f1e5dbdd3ca35536 (patch)
tree871f1f4ed8d23bb8496ef38711769a715c114db8 /drivers/gpu/nvgpu/volt
parent741d78ec45f6c48348743617ba5ae7163c95e49a (diff)
gpu: nvgpu: Update volt pwm source & raw period
- calculate raw period as per pwm source - update pwm source for logic & sram rails. JIRA DNVGPU-123 Change-Id: I50b41d51b6aba760710700522dced7859f815463 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1227626 (cherry picked from commit 6eb5a235dd7bf9031ef1bcfadd6312a2f8758fd4) Reviewed-on: http://git-master/r/1244663 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/volt')
-rw-r--r--drivers/gpu/nvgpu/volt/volt_dev.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c
index 89040658..3a7ed1b5 100644
--- a/drivers/gpu/nvgpu/volt/volt_dev.c
+++ b/drivers/gpu/nvgpu/volt/volt_dev.c
@@ -26,7 +26,6 @@
26#include "include/bios.h" 26#include "include/bios.h"
27#include "volt.h" 27#include "volt.h"
28 28
29#define RAW_PERIOD 160
30#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0 29#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0
31#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1 30#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1
32 31
@@ -257,17 +256,24 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g,
257 256
258 if (ptmp_dev->super.operation_type == 257 if (ptmp_dev->super.operation_type ==
259 CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { 258 CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) {
260 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; 259 if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC)
260 ptmp_dev->source =
261 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0;
262 if (volt_domain == CTRL_VOLT_DOMAIN_SRAM)
263 ptmp_dev->source =
264 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1;
265 ptmp_dev->raw_period =
266 g->ops.clk.get_crystal_clk_hz(g) / frequency_hz;
261 } else if (ptmp_dev->super.operation_type == 267 } else if (ptmp_dev->super.operation_type ==
262 CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) { 268 CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) {
263 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_0; 269 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_0;
270 ptmp_dev->raw_period = 0;
264 } else if (ptmp_dev->super.operation_type == 271 } else if (ptmp_dev->super.operation_type ==
265 CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE) { 272 CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE) {
266 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_1; 273 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_1;
274 ptmp_dev->raw_period = 0;
267 } 275 }
268 276
269 ptmp_dev->raw_period = RAW_PERIOD;
270
271 /* Initialize data for parent class. */ 277 /* Initialize data for parent class. */
272 ptmp_dev->super.super.type = CTRL_VOLT_DEVICE_TYPE_PWM; 278 ptmp_dev->super.super.type = CTRL_VOLT_DEVICE_TYPE_PWM;
273 ptmp_dev->super.volt_domain = volt_domain; 279 ptmp_dev->super.volt_domain = volt_domain;