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authorsmadhavan <smadhavan@nvidia.com>2018-09-14 02:28:41 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-25 00:17:42 -0400
commit3c3f80a687ae95c36341d9bf1753f63dfc4a06af (patch)
tree21f0c537bb7f417756e2c7feca17bdbcd0060702 /drivers/gpu/nvgpu/volt/volt_rail.h
parent75e59e40045c6fbf93c5b828d8a12ba84b573585 (diff)
gpu: nvgpu: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in nvgpu by renaming them to follow the convention,'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: I8a473c6c1a864f3893920d8e06e305095e523d2a Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809082 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/volt/volt_rail.h')
-rw-r--r--drivers/gpu/nvgpu/volt/volt_rail.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.h b/drivers/gpu/nvgpu/volt/volt_rail.h
index 6c667eed..522d635a 100644
--- a/drivers/gpu/nvgpu/volt/volt_rail.h
+++ b/drivers/gpu/nvgpu/volt/volt_rail.h
@@ -21,8 +21,8 @@
21*/ 21*/
22 22
23 23
24#ifndef _VOLT_RAIL_H_ 24#ifndef NVGPU_VOLT_RAIL_H
25#define _VOLT_RAIL_H_ 25#define NVGPU_VOLT_RAIL_H
26 26
27#include "boardobj/boardobj.h" 27#include "boardobj/boardobj.h"
28#include "boardobj/boardobjgrp.h" 28#include "boardobj/boardobjgrp.h"
@@ -87,4 +87,4 @@ u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
87 87
88int volt_rail_sw_setup(struct gk20a *g); 88int volt_rail_sw_setup(struct gk20a *g);
89int volt_rail_pmu_setup(struct gk20a *g); 89int volt_rail_pmu_setup(struct gk20a *g);
90#endif 90#endif /* NVGPU_VOLT_RAIL_H */