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authorSai Nikhil <snikhil@nvidia.com>2018-08-30 04:05:00 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-27 02:35:29 -0400
commitd77785800b2ae4c27354500305303c395a18acf4 (patch)
tree1adc96ba310572d8b63dd2284fb801439616a4c1 /drivers/gpu/nvgpu/volt/volt_rail.c
parent34732a14b22f09d8f9d52f756612178f0313f120 (diff)
gpu: nvgpu: volt: fix MISRA Rule 10.4 Violations
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Ic9a911beb6d161df950ca85eb4813547603a8743 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809751 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/volt/volt_rail.c')
-rw-r--r--drivers/gpu/nvgpu/volt/volt_rail.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c
index 37e85761..caf297f0 100644
--- a/drivers/gpu/nvgpu/volt/volt_rail.c
+++ b/drivers/gpu/nvgpu/volt/volt_rail.c
@@ -105,7 +105,7 @@ static u32 volt_rail_state_init(struct gk20a *g,
105 pvolt_rail->volt_dev_idx_default = CTRL_BOARDOBJ_IDX_INVALID; 105 pvolt_rail->volt_dev_idx_default = CTRL_BOARDOBJ_IDX_INVALID;
106 106
107 for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { 107 for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
108 pvolt_rail->volt_delta_uv[i] = NV_PMU_VOLT_VALUE_0V_IN_UV; 108 pvolt_rail->volt_delta_uv[i] = (int)NV_PMU_VOLT_VALUE_0V_IN_UV;
109 g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i] = 109 g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i] =
110 NV_PMU_VOLT_VALUE_0V_IN_UV; 110 NV_PMU_VOLT_VALUE_0V_IN_UV;
111 } 111 }
@@ -162,7 +162,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g,
162 162
163 for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { 163 for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
164 rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + 164 rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] +
165 g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i]; 165 (int)g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i];
166 } 166 }
167 167
168 status = boardobjgrpmask_export(&prail->volt_dev_mask.super, 168 status = boardobjgrpmask_export(&prail->volt_dev_mask.super,
@@ -225,7 +225,7 @@ u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
225{ 225{
226 switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { 226 switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) {
227 case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: 227 case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
228 if (vbios_volt_domain == 0) { 228 if (vbios_volt_domain == 0U) {
229 return CTRL_VOLT_DOMAIN_LOGIC; 229 return CTRL_VOLT_DOMAIN_LOGIC;
230 } 230 }
231 break; 231 break;
@@ -382,7 +382,7 @@ static int _volt_rail_devgrp_pmudata_instget(struct gk20a *g,
382 382
383 /*check whether pmuboardobjgrp has a valid boardobj in index*/ 383 /*check whether pmuboardobjgrp has a valid boardobj in index*/
384 if (((u32)BIT(idx) & 384 if (((u32)BIT(idx) &
385 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { 385 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) {
386 return -EINVAL; 386 return -EINVAL;
387 } 387 }
388 388
@@ -402,7 +402,7 @@ static int _volt_rail_devgrp_pmustatus_instget(struct gk20a *g,
402 402
403 /*check whether pmuboardobjgrp has a valid boardobj in index*/ 403 /*check whether pmuboardobjgrp has a valid boardobj in index*/
404 if (((u32)BIT(idx) & 404 if (((u32)BIT(idx) &
405 pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { 405 pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) {
406 return -EINVAL; 406 return -EINVAL;
407 } 407 }
408 408