diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-02-14 04:01:01 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-15 02:46:59 -0400 |
commit | d3f96dfa96a8aafe6f5035e2ed24425141e4202e (patch) | |
tree | 05eb958518d5e6d9f31d607d1a9cf2f6e39ce295 /drivers/gpu/nvgpu/volt/volt_rail.c | |
parent | e77ec1a98e6d65eac5b56999af17d51ffca6671f (diff) |
gpu: nvgpu: gv10x volt rail boardobj changes
- Created volt ops under pmu_ver to support volt_set_voltage,
volt_get_voltage & volt_send_load_cmd_to_pmu.
- Renamed volt load, set_voltage & get_voltage gp10x method names.
- Added new volt load, set_voltage & get_voltage methods for gv10x
using RPC & added code to handle ack in pmu_rpc_handler() along
with struct rail_list changes.
- Updated volt ops of gp106 & gv100 to point to respective methods.
- Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to
"struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail"
made changes to update members as needed.
- Added member volt_scale_exp_pwr_equ_idx to
"struct vbios_voltage_rail_table_1x_entry" to read
value from VBIOS table & update rail boardobj set interface.
- Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*"
- Define struct's volt load, set_voltage & get_voltage to execute
volt RPC.
Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1659728
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/volt/volt_rail.c')
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_rail.c | 35 |
1 files changed, 33 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c index f78fc315..3461653f 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/volt/volt_rail.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -34,8 +34,10 @@ u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain) | |||
34 | { | 34 | { |
35 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { | 35 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { |
36 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: | 36 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: |
37 | if (volt_domain == CTRL_BOARDOBJ_IDX_INVALID) | 37 | switch (volt_domain) { |
38 | case CTRL_VOLT_DOMAIN_LOGIC: | ||
38 | return 0; | 39 | return 0; |
40 | } | ||
39 | break; | 41 | break; |
40 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: | 42 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: |
41 | switch (volt_domain) { | 43 | switch (volt_domain) { |
@@ -63,6 +65,22 @@ u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail | |||
63 | status = -EINVAL; | 65 | status = -EINVAL; |
64 | goto exit; | 66 | goto exit; |
65 | } | 67 | } |
68 | } else if (operation_type == | ||
69 | CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN) { | ||
70 | if (pvolt_rail->volt_dev_idx_ipc_vmin == | ||
71 | CTRL_BOARDOBJ_IDX_INVALID) { | ||
72 | pvolt_rail->volt_dev_idx_ipc_vmin = volt_dev_idx; | ||
73 | /* | ||
74 | * Exit on purpose as we do not want to register | ||
75 | * IPC_VMIN device against the rail to avoid | ||
76 | * setting current voltage instead of | ||
77 | * IPC Vmin voltage. | ||
78 | */ | ||
79 | goto exit; | ||
80 | } else { | ||
81 | status = -EINVAL; | ||
82 | goto exit; | ||
83 | } | ||
66 | } else { | 84 | } else { |
67 | goto exit; | 85 | goto exit; |
68 | } | 86 | } |
@@ -136,6 +154,9 @@ static u32 volt_rail_init_pmudata_super(struct gk20a *g, | |||
136 | prail->volt_margin_limit_vfe_equ_idx; | 154 | prail->volt_margin_limit_vfe_equ_idx; |
137 | rail_pmu_data->pwr_equ_idx = prail->pwr_equ_idx; | 155 | rail_pmu_data->pwr_equ_idx = prail->pwr_equ_idx; |
138 | rail_pmu_data->volt_dev_idx_default = prail->volt_dev_idx_default; | 156 | rail_pmu_data->volt_dev_idx_default = prail->volt_dev_idx_default; |
157 | rail_pmu_data->volt_scale_exp_pwr_equ_idx = | ||
158 | prail->volt_scale_exp_pwr_equ_idx; | ||
159 | rail_pmu_data->volt_dev_idx_ipc_vmin = prail->volt_dev_idx_ipc_vmin; | ||
139 | 160 | ||
140 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { | 161 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { |
141 | rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + | 162 | rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + |
@@ -187,6 +208,8 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs) | |||
187 | ptemp_rail->vmin_limit_vfe_equ_idx; | 208 | ptemp_rail->vmin_limit_vfe_equ_idx; |
188 | board_obj_volt_rail_ptr->volt_margin_limit_vfe_equ_idx = | 209 | board_obj_volt_rail_ptr->volt_margin_limit_vfe_equ_idx = |
189 | ptemp_rail->volt_margin_limit_vfe_equ_idx; | 210 | ptemp_rail->volt_margin_limit_vfe_equ_idx; |
211 | board_obj_volt_rail_ptr->volt_scale_exp_pwr_equ_idx = | ||
212 | ptemp_rail->volt_scale_exp_pwr_equ_idx; | ||
190 | 213 | ||
191 | gk20a_dbg_info("Done"); | 214 | gk20a_dbg_info("Done"); |
192 | 215 | ||
@@ -285,6 +308,14 @@ static u32 volt_get_volt_rail_table(struct gk20a *g, | |||
285 | (u8)entry.ov_limit_vfe_equ_idx; | 308 | (u8)entry.ov_limit_vfe_equ_idx; |
286 | 309 | ||
287 | if (header.table_entry_size >= | 310 | if (header.table_entry_size >= |
311 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C) | ||
312 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | ||
313 | (u8)entry.volt_scale_exp_pwr_equ_idx; | ||
314 | else | ||
315 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | ||
316 | CTRL_BOARDOBJ_IDX_INVALID; | ||
317 | |||
318 | if (header.table_entry_size >= | ||
288 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) | 319 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) |
289 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = | 320 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = |
290 | (u8)entry.volt_margin_limit_vfe_equ_idx; | 321 | (u8)entry.volt_margin_limit_vfe_equ_idx; |