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authorSrirangan <smadhavan@nvidia.com>2018-09-04 07:16:40 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-05 23:41:06 -0400
commit3b413d58fa349eca1da9577359546c39effa2c8c (patch)
tree2bb45c9253fb6a5a18afa6d1c12ffeca79effd8e /drivers/gpu/nvgpu/volt/volt_pmu.c
parent7405cd9a6dcd22d04f48be07be4839c735994ada (diff)
gpu: nvgpu: volt: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces by introducing the braces. JIRA NVGPU-671 Change-Id: I938f49b2d1d042dc96573e1a579fe82909a679ab Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812421 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/volt/volt_pmu.c')
-rw-r--r--drivers/gpu/nvgpu/volt/volt_pmu.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c
index bd9177ff..6d92686c 100644
--- a/drivers/gpu/nvgpu/volt/volt_pmu.c
+++ b/drivers/gpu/nvgpu/volt/volt_pmu.c
@@ -54,8 +54,9 @@ static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
54 return; 54 return;
55 } 55 }
56 56
57 if (phandlerparams->prpc_call->b_supported) 57 if (phandlerparams->prpc_call->b_supported) {
58 phandlerparams->success = 1; 58 phandlerparams->success = 1;
59 }
59} 60}
60 61
61 62
@@ -124,10 +125,11 @@ u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g)
124 rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD; 125 rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD;
125 126
126 status = volt_pmu_rpc_execute(g, &rpc_call); 127 status = volt_pmu_rpc_execute(g, &rpc_call);
127 if (status) 128 if (status) {
128 nvgpu_err(g, 129 nvgpu_err(g,
129 "Error while executing LOAD RPC: status = 0x%08x.", 130 "Error while executing LOAD RPC: status = 0x%08x.",
130 status); 131 status);
132 }
131 133
132 return status; 134 return status;
133} 135}
@@ -241,9 +243,10 @@ static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
241 } 243 }
242 244
243 /* Convert the client ID to index. */ 245 /* Convert the client ID to index. */
244 if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ) 246 if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ) {
245 policy_idx = 247 policy_idx =
246 pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx; 248 pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx;
249 }
247 else { 250 else {
248 status = -EINVAL; 251 status = -EINVAL;
249 goto exit; 252 goto exit;
@@ -257,9 +260,10 @@ static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
257 260
258 /* Execute the voltage change request via PMU RPC. */ 261 /* Execute the voltage change request via PMU RPC. */
259 status = volt_pmu_rpc_execute(g, &rpc_call); 262 status = volt_pmu_rpc_execute(g, &rpc_call);
260 if (status) 263 if (status) {
261 nvgpu_err(g, 264 nvgpu_err(g,
262 "Error while executing VOLT_POLICY_SET_VOLTAGE RPC"); 265 "Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
266 }
263 267
264exit: 268exit:
265 return status; 269 return status;