diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-05-24 15:31:57 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:07 -0400 |
commit | ed65f1f26e2d0ca4a491215297b61d25b0c1493b (patch) | |
tree | ad4ce439a0f77fe89f9138e6f4284aeaa996b4c8 /drivers/gpu/nvgpu/vgpu | |
parent | 4eae06299ba35e3f6a48eef4a19cde6d1c374deb (diff) |
gpu: nvgpu: Move setting priv interrupt to priv_ring
Registers to set priv interrupts are in priv_ring, but the code was
in bus HAL. Move the code and related HALs to priv_ring instead.
JIRA NVGPU-588
Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730889
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 3f6d4e0f..f4a87a74 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -529,8 +529,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
529 | .read_ptimer = vgpu_read_ptimer, | 529 | .read_ptimer = vgpu_read_ptimer, |
530 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | 530 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, |
531 | .bar1_bind = gk20a_bus_bar1_bind, | 531 | .bar1_bind = gk20a_bus_bar1_bind, |
532 | .set_ppriv_timeout_settings = | ||
533 | gk20a_bus_set_ppriv_timeout_settings, | ||
534 | }, | 532 | }, |
535 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 533 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
536 | .css = { | 534 | .css = { |
@@ -548,6 +546,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
548 | }, | 546 | }, |
549 | .priv_ring = { | 547 | .priv_ring = { |
550 | .isr = gp10b_priv_ring_isr, | 548 | .isr = gp10b_priv_ring_isr, |
549 | .set_ppriv_timeout_settings = | ||
550 | gk20a_priv_set_timeout_settings, | ||
551 | }, | 551 | }, |
552 | .fuse = { | 552 | .fuse = { |
553 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, | 553 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 0a48e1ae..deecc0d8 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -577,8 +577,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
577 | .read_ptimer = vgpu_read_ptimer, | 577 | .read_ptimer = vgpu_read_ptimer, |
578 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | 578 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, |
579 | .bar1_bind = NULL, | 579 | .bar1_bind = NULL, |
580 | .set_ppriv_timeout_settings = | ||
581 | gk20a_bus_set_ppriv_timeout_settings, | ||
582 | }, | 580 | }, |
583 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 581 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
584 | .css = { | 582 | .css = { |
@@ -596,6 +594,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
596 | }, | 594 | }, |
597 | .priv_ring = { | 595 | .priv_ring = { |
598 | .isr = gp10b_priv_ring_isr, | 596 | .isr = gp10b_priv_ring_isr, |
597 | .set_ppriv_timeout_settings = | ||
598 | gk20a_priv_set_timeout_settings, | ||
599 | }, | 599 | }, |
600 | .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, | 600 | .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, |
601 | .get_litter_value = gv11b_get_litter_value, | 601 | .get_litter_value = gv11b_get_litter_value, |