gpu: nvgpu: add tsg support for vgpu

- make tsg_gk20a.c call HAL for enable/disable channels
- add preempt_tsg HAL callbacks
- add tsg bind/unbind channel HAL callbacks
- add according tsg callbacks for vgpu

Bug 1702773
JIRA VFND-1003

Change-Id: I2cba74b3ebd3920ef09219a168e6433d9574dbe8
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1144932
(cherry picked from commit c3787de7d38651d46969348f5acae2ba86b31ec7)
Reviewed-on: http://git-master/r/1126942
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 files changed, 177 insertions, 21 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 8fcc7cc1..fb19db4a 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -410,6 +410,30 @@ static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 hw_chid)
         return err;
 }
 
+static int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid)
+{
+        struct gk20a_platform *platform = gk20a_get_platform(g->dev);
+        struct tegra_vgpu_cmd_msg msg;
+        struct tegra_vgpu_tsg_preempt_params *p =
+                        &msg.params.tsg_preempt;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        msg.cmd = TEGRA_VGPU_CMD_TSG_PREEMPT;
+        msg.handle = platform->virt_handle;
+        p->tsg_id = tsgid;
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        err = err ? err : msg.ret;
+
+        if (err) {
+                gk20a_err(dev_from_gk20a(g),
+                        "preempt tsg %u failed\n", tsgid);
+        }
+
+        return err;
+}
+
 static int vgpu_submit_runlist(u64 handle, u8 runlist_id, u16 *runlist,
                         u32 num_entries)
 {
@@ -680,6 +704,7 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops)
         gops->fifo.free_inst = vgpu_channel_free_inst;
         gops->fifo.setup_ramfc = vgpu_channel_setup_ramfc;
         gops->fifo.preempt_channel = vgpu_fifo_preempt_channel;
+        gops->fifo.preempt_tsg = vgpu_fifo_preempt_tsg;
         gops->fifo.update_runlist = vgpu_fifo_update_runlist;
         gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle;
         gops->fifo.channel_set_priority = vgpu_channel_set_priority;
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index b9490ac9..f395ac1e 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -445,6 +445,26 @@ static int vgpu_gr_ch_bind_gr_ctx(struct channel_gk20a *c)
         return err;
 }
 
+static int vgpu_gr_tsg_bind_gr_ctx(struct tsg_gk20a *tsg)
+{
+        struct gk20a_platform *platform = gk20a_get_platform(tsg->g->dev);
+        struct gr_ctx_desc *gr_ctx = tsg->tsg_gr_ctx;
+        struct tegra_vgpu_cmd_msg msg = {0};
+        struct tegra_vgpu_tsg_bind_gr_ctx_params *p =
+                                        &msg.params.tsg_bind_gr_ctx;
+        int err;
+
+        msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_GR_CTX;
+        msg.handle = platform->virt_handle;
+        p->tsg_id = tsg->tsgid;
+        p->gr_ctx_handle = gr_ctx->virt_ctx;
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        err = err ? err : msg.ret;
+        WARN_ON(err);
+
+        return err;
+}
+
 static int vgpu_gr_alloc_obj_ctx(struct channel_gk20a  *c,
                                 struct nvgpu_alloc_obj_ctx_args *args)
 {
@@ -472,32 +492,58 @@ static int vgpu_gr_alloc_obj_ctx(struct channel_gk20a  *c,
         }
         c->obj_class = args->class_num;
 
-        /* FIXME: add TSG support */
         if (gk20a_is_channel_marked_as_tsg(c))
                 tsg = &f->tsg[c->tsgid];
 
-        /* allocate gr ctx buffer */
-        if (!ch_ctx->gr_ctx) {
-                err = g->ops.gr.alloc_gr_ctx(g, &c->ch_ctx.gr_ctx,
-                                        c->vm,
-                                        args->class_num,
-                                        args->flags);
-                if (!err)
-                        err = vgpu_gr_ch_bind_gr_ctx(c);
+        if (!tsg) {
+                /* allocate gr ctx buffer */
+                if (!ch_ctx->gr_ctx) {
+                        err = g->ops.gr.alloc_gr_ctx(g, &c->ch_ctx.gr_ctx,
+                                                c->vm,
+                                                args->class_num,
+                                                args->flags);
+                        if (!err)
+                                err = vgpu_gr_ch_bind_gr_ctx(c);
+                        if (err) {
+                                gk20a_err(dev_from_gk20a(g),
+                                        "fail to allocate gr ctx buffer");
+                                goto out;
+                        }
+                } else {
+                        /*TBD: needs to be more subtle about which is
+                         * being allocated as some are allowed to be
+                         * allocated along same channel */
+                        gk20a_err(dev_from_gk20a(g),
+                                "too many classes alloc'd on same channel");
+                        err = -EINVAL;
+                        goto out;
+                }
+        } else {
+                if (!tsg->tsg_gr_ctx) {
+                        tsg->vm = c->vm;
+                        gk20a_vm_get(tsg->vm);
+                        err = g->ops.gr.alloc_gr_ctx(g, &tsg->tsg_gr_ctx,
+                                                c->vm,
+                                                args->class_num,
+                                                args->flags);
+                        if (!err)
+                                err = vgpu_gr_tsg_bind_gr_ctx(tsg);
+                        if (err) {
+                                gk20a_err(dev_from_gk20a(g),
+                                        "fail to allocate TSG gr ctx buffer, err=%d", err);
+                                gk20a_vm_put(tsg->vm);
+                                tsg->vm = NULL;
+                                goto out;
+                        }
+                }
 
+                ch_ctx->gr_ctx = tsg->tsg_gr_ctx;
+                err = vgpu_gr_ch_bind_gr_ctx(c);
                 if (err) {
                         gk20a_err(dev_from_gk20a(g),
-                                "fail to allocate gr ctx buffer");
+                                "fail to bind gr ctx buffer");
                         goto out;
                 }
-        } else {
-                /*TBD: needs to be more subtle about which is
-                 * being allocated as some are allowed to be
-                 * allocated along same channel */
-                gk20a_err(dev_from_gk20a(g),
-                        "too many classes alloc'd on same channel");
-                err = -EINVAL;
-                goto out;
         }
 
         /* commit gr ctx buffer */
diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
new file mode 100644
index 00000000..9245693d
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/tegra_vgpu.h>
+
+#include "gk20a/gk20a.h"
+#include "gk20a/channel_gk20a.h"
+#include "gk20a/platform_gk20a.h"
+#include "gk20a/tsg_gk20a.h"
+#include "vgpu.h"
+
+static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
+                        struct channel_gk20a *ch)
+{
+        struct gk20a_platform *platform = gk20a_get_platform(tsg->g->dev);
+        struct tegra_vgpu_cmd_msg msg = {};
+        struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
+                                &msg.params.tsg_bind_unbind_channel;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        err = gk20a_tsg_bind_channel(tsg, ch);
+        if (err)
+                return err;
+
+        msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL;
+        msg.handle = platform->virt_handle;
+        p->tsg_id = tsg->tsgid;
+        p->ch_handle = ch->virt_ctx;
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        err = err ? err : msg.ret;
+        if (err) {
+                gk20a_err(dev_from_gk20a(tsg->g),
+                        "vgpu_tsg_bind_channel failed, ch %d tsgid %d",
+                        ch->hw_chid, tsg->tsgid);
+                gk20a_tsg_unbind_channel(ch);
+        }
+
+        return err;
+}
+
+static int vgpu_tsg_unbind_channel(struct channel_gk20a *ch)
+{
+        struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev);
+        struct tegra_vgpu_cmd_msg msg = {};
+        struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
+                                &msg.params.tsg_bind_unbind_channel;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        err = gk20a_tsg_unbind_channel(ch);
+        if (err)
+                return err;
+
+        msg.cmd = TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL;
+        msg.handle = platform->virt_handle;
+        p->ch_handle = ch->virt_ctx;
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        err = err ? err : msg.ret;
+        WARN_ON(err);
+
+        return err;
+}
+
+void vgpu_init_tsg_ops(struct gpu_ops *gops)
+{
+        gops->fifo.tsg_bind_channel = vgpu_tsg_bind_channel;
+        gops->fifo.tsg_unbind_channel = vgpu_tsg_unbind_channel;
+}
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c
index 3c06652b..4948d246 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.c
@@ -268,6 +268,7 @@ void vgpu_init_hal_common(struct gk20a *g)
         vgpu_init_mm_ops(gops);
         vgpu_init_debug_ops(gops);
         vgpu_init_fecs_trace_ops(gops);
+        vgpu_init_tsg_ops(gops);
         gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
 }
 
@@ -340,8 +341,6 @@ int vgpu_pm_finalize_poweron(struct device *dev)
                 goto done;
         }
 
-        g->gpu_characteristics.flags &= ~NVGPU_GPU_FLAGS_SUPPORT_TSG;
-
         gk20a_ctxsw_trace_init(g);
         gk20a_channel_resume(g);
 
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h
index 32f4b110..fdd0a54c 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.h
@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU Interfaces
  *
- * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -47,6 +47,7 @@ void vgpu_init_gr_ops(struct gpu_ops *gops);
 void vgpu_init_ltc_ops(struct gpu_ops *gops);
 void vgpu_init_mm_ops(struct gpu_ops *gops);
 void vgpu_init_debug_ops(struct gpu_ops *gops);
+void vgpu_init_tsg_ops(struct gpu_ops *gops);
 int vgpu_init_mm_support(struct gk20a *g);
 int vgpu_init_gr_support(struct gk20a *g);
 int vgpu_init_fifo_support(struct gk20a *g);