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authorPeter Daifuku <pdaifuku@nvidia.com>2019-01-25 18:06:46 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2019-01-31 01:18:04 -0500
commitd39781054f63a510b0eaccee5e1099d7ae6ce132 (patch)
tree484198d2d4be323f6db334bacd764498311b004f /drivers/gpu/nvgpu/vgpu
parent61bb9dc40395257fa1dc15d267496e3deb32a3e5 (diff)
gpu: nvgpu: allocate ctxsw buffers once only
In *_set_ctxsw_preemption_mode, only allocate buffers the first time through. Bug 200418468 Change-Id: I22d06463416615b9a9d671c32b6fe76b602a2623 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2004301 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c57
1 files changed, 31 insertions, 26 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
index 8110902f..eb6f4408 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -140,47 +140,52 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
140 nvgpu_log_info(g, "gfxp context attrib cb size=%d", 140 nvgpu_log_info(g, "gfxp context attrib cb size=%d",
141 attrib_cb_size); 141 attrib_cb_size);
142 142
143 err = gr_gp10b_alloc_buffer(vm, 143 /* Only allocate buffers the first time through */
144 if (!nvgpu_mem_is_valid(&gr_ctx->preempt_ctxsw_buffer)) {
145 err = gr_gp10b_alloc_buffer(vm,
144 g->gr.ctx_vars.preempt_image_size, 146 g->gr.ctx_vars.preempt_image_size,
145 &gr_ctx->preempt_ctxsw_buffer); 147 &gr_ctx->preempt_ctxsw_buffer);
146 if (err) { 148 if (err) {
147 err = -ENOMEM; 149 err = -ENOMEM;
148 goto fail; 150 goto fail;
151 }
152
153 err = gr_gp10b_alloc_buffer(vm,
154 spill_size,
155 &gr_ctx->spill_ctxsw_buffer);
156 if (err) {
157 err = -ENOMEM;
158 goto fail;
159 }
160 err = gr_gp10b_alloc_buffer(vm,
161 pagepool_size,
162 &gr_ctx->pagepool_ctxsw_buffer);
163 if (err) {
164 err = -ENOMEM;
165 goto fail;
166 }
167 err = gr_gp10b_alloc_buffer(vm,
168 attrib_cb_size,
169 &gr_ctx->betacb_ctxsw_buffer);
170 if (err) {
171 err = -ENOMEM;
172 goto fail;
173 }
149 } 174 }
175
150 desc = &gr_ctx->preempt_ctxsw_buffer; 176 desc = &gr_ctx->preempt_ctxsw_buffer;
151 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; 177 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va;
152 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; 178 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size;
153 179
154 err = gr_gp10b_alloc_buffer(vm,
155 spill_size,
156 &gr_ctx->spill_ctxsw_buffer);
157 if (err) {
158 err = -ENOMEM;
159 goto fail;
160 }
161 desc = &gr_ctx->spill_ctxsw_buffer; 180 desc = &gr_ctx->spill_ctxsw_buffer;
162 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; 181 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va;
163 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; 182 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size;
164 183
165 err = gr_gp10b_alloc_buffer(vm,
166 pagepool_size,
167 &gr_ctx->pagepool_ctxsw_buffer);
168 if (err) {
169 err = -ENOMEM;
170 goto fail;
171 }
172 desc = &gr_ctx->pagepool_ctxsw_buffer; 184 desc = &gr_ctx->pagepool_ctxsw_buffer;
173 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = 185 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] =
174 desc->gpu_va; 186 desc->gpu_va;
175 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; 187 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size;
176 188
177 err = gr_gp10b_alloc_buffer(vm,
178 attrib_cb_size,
179 &gr_ctx->betacb_ctxsw_buffer);
180 if (err) {
181 err = -ENOMEM;
182 goto fail;
183 }
184 desc = &gr_ctx->betacb_ctxsw_buffer; 189 desc = &gr_ctx->betacb_ctxsw_buffer;
185 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = 190 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] =
186 desc->gpu_va; 191 desc->gpu_va;