diff options
author | Richard Zhao <rizhao@nvidia.com> | 2018-05-31 19:08:05 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:06 -0400 |
commit | c5cf398b2aac7c725492033d02b1d9e778acd592 (patch) | |
tree | 7d17b9b07e02eba6ab205914738056065bd3bfb8 /drivers/gpu/nvgpu/vgpu | |
parent | 2318e66a59e4e25240513fe7d267fc63b7353a15 (diff) |
gpu: nvgpu: vgpu: clean up nonstall isrs
It has moved to use TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUP, removing legacy
isrs.
Jira EVLR-2696
Change-Id: Ie977bba59c0af8589989d872150c3f9b2080854a
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1736399
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/ce2_vgpu.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 9 |
4 files changed, 0 insertions, 60 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c index 563c3a2b..aa3783b9 100644 --- a/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c | |||
@@ -27,23 +27,6 @@ | |||
27 | #include <nvgpu/bug.h> | 27 | #include <nvgpu/bug.h> |
28 | #include <nvgpu/vgpu/vgpu.h> | 28 | #include <nvgpu/vgpu/vgpu.h> |
29 | 29 | ||
30 | int vgpu_ce2_nonstall_isr(struct gk20a *g, | ||
31 | struct tegra_vgpu_ce2_nonstall_intr_info *info) | ||
32 | { | ||
33 | nvgpu_log_fn(g, " "); | ||
34 | |||
35 | switch (info->type) { | ||
36 | case TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE: | ||
37 | g->ops.semaphore_wakeup(g, true); | ||
38 | break; | ||
39 | default: | ||
40 | WARN_ON(1); | ||
41 | break; | ||
42 | } | ||
43 | |||
44 | return 0; | ||
45 | } | ||
46 | |||
47 | u32 vgpu_ce_get_num_pce(struct gk20a *g) | 30 | u32 vgpu_ce_get_num_pce(struct gk20a *g) |
48 | { | 31 | { |
49 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | 32 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index eb25cf3a..b0388fae 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -753,23 +753,6 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) | |||
753 | return 0; | 753 | return 0; |
754 | } | 754 | } |
755 | 755 | ||
756 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | ||
757 | struct tegra_vgpu_fifo_nonstall_intr_info *info) | ||
758 | { | ||
759 | nvgpu_log_fn(g, " "); | ||
760 | |||
761 | switch (info->type) { | ||
762 | case TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL: | ||
763 | g->ops.semaphore_wakeup(g, false); | ||
764 | break; | ||
765 | default: | ||
766 | WARN_ON(1); | ||
767 | break; | ||
768 | } | ||
769 | |||
770 | return 0; | ||
771 | } | ||
772 | |||
773 | u32 vgpu_fifo_default_timeslice_us(struct gk20a *g) | 756 | u32 vgpu_fifo_default_timeslice_us(struct gk20a *g) |
774 | { | 757 | { |
775 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | 758 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); |
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index a512c36b..2ae615bf 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -987,23 +987,6 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) | |||
987 | return 0; | 987 | return 0; |
988 | } | 988 | } |
989 | 989 | ||
990 | int vgpu_gr_nonstall_isr(struct gk20a *g, | ||
991 | struct tegra_vgpu_gr_nonstall_intr_info *info) | ||
992 | { | ||
993 | nvgpu_log_fn(g, " "); | ||
994 | |||
995 | switch (info->type) { | ||
996 | case TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE: | ||
997 | g->ops.semaphore_wakeup(g, true); | ||
998 | break; | ||
999 | default: | ||
1000 | WARN_ON(1); | ||
1001 | break; | ||
1002 | } | ||
1003 | |||
1004 | return 0; | ||
1005 | } | ||
1006 | |||
1007 | int vgpu_gr_set_sm_debug_mode(struct gk20a *g, | 990 | int vgpu_gr_set_sm_debug_mode(struct gk20a *g, |
1008 | struct channel_gk20a *ch, u64 sms, bool enable) | 991 | struct channel_gk20a *ch, u64 sms, bool enable) |
1009 | { | 992 | { |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index 17e80cd7..2bdef427 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -164,17 +164,8 @@ int vgpu_intr_thread(void *dev_id) | |||
164 | case TEGRA_VGPU_EVENT_INTR: | 164 | case TEGRA_VGPU_EVENT_INTR: |
165 | if (msg->unit == TEGRA_VGPU_INTR_GR) | 165 | if (msg->unit == TEGRA_VGPU_INTR_GR) |
166 | vgpu_gr_isr(g, &msg->info.gr_intr); | 166 | vgpu_gr_isr(g, &msg->info.gr_intr); |
167 | else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR) | ||
168 | vgpu_gr_nonstall_isr(g, | ||
169 | &msg->info.gr_nonstall_intr); | ||
170 | else if (msg->unit == TEGRA_VGPU_INTR_FIFO) | 167 | else if (msg->unit == TEGRA_VGPU_INTR_FIFO) |
171 | vgpu_fifo_isr(g, &msg->info.fifo_intr); | 168 | vgpu_fifo_isr(g, &msg->info.fifo_intr); |
172 | else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_FIFO) | ||
173 | vgpu_fifo_nonstall_isr(g, | ||
174 | &msg->info.fifo_nonstall_intr); | ||
175 | else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_CE2) | ||
176 | vgpu_ce2_nonstall_isr(g, | ||
177 | &msg->info.ce2_nonstall_intr); | ||
178 | break; | 169 | break; |
179 | #ifdef CONFIG_GK20A_CTXSW_TRACE | 170 | #ifdef CONFIG_GK20A_CTXSW_TRACE |
180 | case TEGRA_VGPU_EVENT_FECS_TRACE: | 171 | case TEGRA_VGPU_EVENT_FECS_TRACE: |