diff options
author | Vinod G <vinodg@nvidia.com> | 2018-08-08 02:09:30 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-25 05:10:43 -0400 |
commit | bfe65407bde2b5d0776724301e215c6553c989f3 (patch) | |
tree | f68a01361052afe1c30a0c6dcd5d359b762e647a /drivers/gpu/nvgpu/vgpu | |
parent | 3bd47da0954d3486d9ccd3c396f84445918f82b4 (diff) |
gpu: nvgpu: Read sm error ioctl support for tsg
Add READ_SM_ERROR IOCTL support to TSG level.
Moved the struct to save the sm_error details
from gr to tsg as the sm_error support is context
based, not global.
Also corrected MISRA 21.1 error in header file.
nvgpu_dbg_gpu_ioctl_write_single_sm_error_state and
nvgpu_dbg_gpu_ioctl_read_single_sm_error_state
functions are modified to use the tsg struct
nvgpu_tsg_sm_error_state.
Bug 200412642
Change-Id: I9e334b059078a4bb0e360b945444cc4bf1cc56ec
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794856
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index fa64cb82..9ee57fb4 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -882,9 +882,6 @@ static void vgpu_remove_gr_support(struct gr_gk20a *gr) | |||
882 | 882 | ||
883 | gk20a_comptag_allocator_destroy(gr->g, &gr->comp_tags); | 883 | gk20a_comptag_allocator_destroy(gr->g, &gr->comp_tags); |
884 | 884 | ||
885 | nvgpu_kfree(gr->g, gr->sm_error_states); | ||
886 | gr->sm_error_states = NULL; | ||
887 | |||
888 | nvgpu_kfree(gr->g, gr->gpc_tpc_mask); | 885 | nvgpu_kfree(gr->g, gr->gpc_tpc_mask); |
889 | gr->gpc_tpc_mask = NULL; | 886 | gr->gpc_tpc_mask = NULL; |
890 | 887 | ||
@@ -935,14 +932,6 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g) | |||
935 | nvgpu_mutex_init(&gr->ctx_mutex); | 932 | nvgpu_mutex_init(&gr->ctx_mutex); |
936 | nvgpu_spinlock_init(&gr->ch_tlb_lock); | 933 | nvgpu_spinlock_init(&gr->ch_tlb_lock); |
937 | 934 | ||
938 | gr->sm_error_states = nvgpu_kzalloc(g, | ||
939 | sizeof(struct nvgpu_gr_sm_error_state) * | ||
940 | gr->no_of_sm); | ||
941 | if (!gr->sm_error_states) { | ||
942 | err = -ENOMEM; | ||
943 | goto clean_up; | ||
944 | } | ||
945 | |||
946 | gr->remove_support = vgpu_remove_gr_support; | 935 | gr->remove_support = vgpu_remove_gr_support; |
947 | gr->sw_ready = true; | 936 | gr->sw_ready = true; |
948 | 937 | ||
@@ -1152,12 +1141,17 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1152 | int vgpu_gr_clear_sm_error_state(struct gk20a *g, | 1141 | int vgpu_gr_clear_sm_error_state(struct gk20a *g, |
1153 | struct channel_gk20a *ch, u32 sm_id) | 1142 | struct channel_gk20a *ch, u32 sm_id) |
1154 | { | 1143 | { |
1155 | struct gr_gk20a *gr = &g->gr; | ||
1156 | struct tegra_vgpu_cmd_msg msg; | 1144 | struct tegra_vgpu_cmd_msg msg; |
1157 | struct tegra_vgpu_clear_sm_error_state *p = | 1145 | struct tegra_vgpu_clear_sm_error_state *p = |
1158 | &msg.params.clear_sm_error_state; | 1146 | &msg.params.clear_sm_error_state; |
1147 | struct tsg_gk20a *tsg; | ||
1159 | int err; | 1148 | int err; |
1160 | 1149 | ||
1150 | tsg = tsg_gk20a_from_ch(ch); | ||
1151 | if (!tsg) { | ||
1152 | return -EINVAL; | ||
1153 | } | ||
1154 | |||
1161 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 1155 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
1162 | msg.cmd = TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE; | 1156 | msg.cmd = TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE; |
1163 | msg.handle = vgpu_get_handle(g); | 1157 | msg.handle = vgpu_get_handle(g); |
@@ -1167,7 +1161,7 @@ int vgpu_gr_clear_sm_error_state(struct gk20a *g, | |||
1167 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 1161 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
1168 | WARN_ON(err || msg.ret); | 1162 | WARN_ON(err || msg.ret); |
1169 | 1163 | ||
1170 | memset(&gr->sm_error_states[sm_id], 0, sizeof(*gr->sm_error_states)); | 1164 | memset(&tsg->sm_error_states[sm_id], 0, sizeof(*tsg->sm_error_states)); |
1171 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 1165 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
1172 | 1166 | ||
1173 | return err ? err : msg.ret; | 1167 | return err ? err : msg.ret; |
@@ -1264,7 +1258,8 @@ int vgpu_gr_resume_contexts(struct gk20a *g, | |||
1264 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | 1258 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, |
1265 | struct tegra_vgpu_sm_esr_info *info) | 1259 | struct tegra_vgpu_sm_esr_info *info) |
1266 | { | 1260 | { |
1267 | struct nvgpu_gr_sm_error_state *sm_error_states; | 1261 | struct nvgpu_tsg_sm_error_state *sm_error_states; |
1262 | struct tsg_gk20a *tsg; | ||
1268 | 1263 | ||
1269 | if (info->sm_id >= g->gr.no_of_sm) { | 1264 | if (info->sm_id >= g->gr.no_of_sm) { |
1270 | nvgpu_err(g, "invalid smd_id %d / %d", | 1265 | nvgpu_err(g, "invalid smd_id %d / %d", |
@@ -1272,9 +1267,20 @@ void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | |||
1272 | return; | 1267 | return; |
1273 | } | 1268 | } |
1274 | 1269 | ||
1270 | if (info->tsg_id >= g->fifo.num_channels) { | ||
1271 | nvgpu_err(g, "invalid tsg_id in sm esr event"); | ||
1272 | return; | ||
1273 | } | ||
1274 | |||
1275 | tsg = &g->fifo.tsg[info->tsg_id]; | ||
1276 | if (tsg == NULL) { | ||
1277 | nvgpu_err(g, "invalid tsg"); | ||
1278 | return; | ||
1279 | } | ||
1280 | |||
1275 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 1281 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
1276 | 1282 | ||
1277 | sm_error_states = &g->gr.sm_error_states[info->sm_id]; | 1283 | sm_error_states = &tsg->sm_error_states[info->sm_id]; |
1278 | 1284 | ||
1279 | sm_error_states->hww_global_esr = info->hww_global_esr; | 1285 | sm_error_states->hww_global_esr = info->hww_global_esr; |
1280 | sm_error_states->hww_warp_esr = info->hww_warp_esr; | 1286 | sm_error_states->hww_warp_esr = info->hww_warp_esr; |