diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-05-10 19:26:40 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-31 13:48:10 -0400 |
commit | b0ffd2f0657a11c2fcd7470430465c77ca5c73b9 (patch) | |
tree | eaf8570dc4436f0fd8d97f90996bf06bc61a749f /drivers/gpu/nvgpu/vgpu | |
parent | 7a134457a840118ed02967a3c0bc4b4f248837ea (diff) |
nvgpu: vgpu: add tsg set interleave support
added a new cmd to support setting tsg interleave level.
Bug 1702773
VFND-1492
Change-Id: Idd9b9c59180b156293ddfc4e2b879d0ea6908388
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1145024
(cherry picked from commit 0929ff1089fbc331b07e17073a46fda4086ae785)
Reviewed-on: http://git-master/r/1150706
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index fb19db4a..0895b757 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -560,6 +560,28 @@ static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) | |||
560 | return err ? err : msg.ret; | 560 | return err ? err : msg.ret; |
561 | } | 561 | } |
562 | 562 | ||
563 | static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, | ||
564 | u32 tsgid, | ||
565 | u32 runlist_id, | ||
566 | u32 new_level) | ||
567 | { | ||
568 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
569 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
570 | struct tegra_vgpu_tsg_runlist_interleave_params *p = | ||
571 | &msg.params.tsg_interleave; | ||
572 | int err; | ||
573 | |||
574 | gk20a_dbg_fn(""); | ||
575 | |||
576 | msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE; | ||
577 | msg.handle = platform->virt_handle; | ||
578 | p->tsg_id = tsgid; | ||
579 | p->level = new_level; | ||
580 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
581 | WARN_ON(err || msg.ret); | ||
582 | return err ? err : msg.ret; | ||
583 | } | ||
584 | |||
563 | static int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | 585 | static int vgpu_fifo_set_runlist_interleave(struct gk20a *g, |
564 | u32 id, | 586 | u32 id, |
565 | bool is_tsg, | 587 | bool is_tsg, |
@@ -575,9 +597,9 @@ static int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | |||
575 | 597 | ||
576 | gk20a_dbg_fn(""); | 598 | gk20a_dbg_fn(""); |
577 | 599 | ||
578 | /* FIXME: add support for TSGs */ | ||
579 | if (is_tsg) | 600 | if (is_tsg) |
580 | return -ENOSYS; | 601 | return vgpu_fifo_tsg_set_runlist_interleave(g, id, |
602 | runlist_id, new_level); | ||
581 | 603 | ||
582 | ch = &g->fifo.channel[id]; | 604 | ch = &g->fifo.channel[id]; |
583 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE; | 605 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE; |